Hi Jiang,
On 07/11/2019 08:00, Jian-Hong Pan wrote:
> Raspberry Pi's memory address & size cells are defined in FDT's root
> node. So, original fdtdec_decode_ram_size() having the cells in memory
> node will get wrong size cells which misleads memory's reg parsing and
> have wrong memory banks.
> This patch provides new decode_ram_size() to parse the memory's reg in
> FDT for Raspberry Pi 4.
>
Thanks for your patch. I think what you try to fix is already fixed in
v2020.01-rc1 with the following commits:
7a3f15e718 ("dm: Fix default address cells return value")
8076fc298e ("libfdt: Allow #size-cells of 0")
0ba41ce1b7 ("libfdt: return correct value if #size-cells property is not
present")
ce2dae3a44 ("libfdt: fdt_address_cells() and fdt_size_cells()")
Regards,
Matthias
> Fixes: commit 9de5b89e4c89 ("rpi4: enable dram bank initialization")
> Signed-off-by: Jian-Hong Pan <jian-h...@endlessm.com>
> ---
> board/raspberrypi/rpi/rpi.c | 60 +++++++++++++++++++++++++++++++++++--
> 1 file changed, 58 insertions(+), 2 deletions(-)
>
> diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c
> index 9e0abdda31..419fb61db5 100644
> --- a/board/raspberrypi/rpi/rpi.c
> +++ b/board/raspberrypi/rpi/rpi.c
> @@ -314,10 +314,66 @@ int dram_init(void)
>
> #ifdef CONFIG_OF_BOARD
> #ifdef CONFIG_BCM2711
> +static int decode_ram_size(const void *blob, phys_size_t *sizep, bd_t *bd)
> +{
> + int addr_cells, size_cells;
> + u64 total_size, size, addr;
> + const u32 *cell;
> + int node;
> + int bank;
> + int len;
> +
> + /* Raspberry Pi's address and size cells are defined in root node */
> + addr_cells = fdt_address_cells(blob, 0);
> + size_cells = fdt_size_cells(blob, 0);
> +
> + node = fdt_path_offset(blob, "/memory");
> + if (node < 0) {
> + debug("No /memory node found\n");
> + return -ENOENT;
> + }
> +
> + cell = fdt_getprop(blob, node, "reg", &len);
> + if (!cell) {
> + debug("No reg property found\n");
> + return -ENOENT;
> + }
> +
> + if (bd) {
> + memset(bd->bi_dram, '\0', sizeof(bd->bi_dram[0]) *
> + CONFIG_NR_DRAM_BANKS);
> + }
> +
> + total_size = 0;
> + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
> + addr = 0;
> + if (addr_cells == 2)
> + addr += (u64)fdt32_to_cpu(*cell++) << 32UL;
> + addr += fdt32_to_cpu(*cell++);
> + if (bd)
> + bd->bi_dram[bank].start = addr;
> +
> + size = 0;
> + if (size_cells == 2)
> + size += (u64)fdt32_to_cpu(*cell++) << 32UL;
> + size += fdt32_to_cpu(*cell++);
> + if (bd)
> + bd->bi_dram[bank].size = size;
> +
> + total_size += size;
> + }
> +
> + debug("Memory size %llu\n", total_size);
> + if (sizep)
> + *sizep = (phys_size_t)total_size;
> +
> + return 0;
> +}
> +
> int dram_init_banksize(void)
> {
> - return fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,
> - (phys_size_t *)&gd->ram_size, gd->bd);
> + return decode_ram_size(gd->fdt_blob, (phys_size_t *)&gd->ram_size,
> + gd->bd);
> }
> #endif
> #endif
>
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