Signed-off-by: Giulio Benetti <giulio.bene...@benettiengineering.com>
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/imxrt1050-evk.dts | 124 ++++++++
arch/arm/dts/imxrt1050.dtsi | 73 +++++
arch/arm/mach-imx/imxrt/Kconfig | 11 +
board/freescale/imxrt1050-evk/Kconfig | 19 ++
board/freescale/imxrt1050-evk/MAINTAINERS | 6 +
board/freescale/imxrt1050-evk/Makefile | 6 +
board/freescale/imxrt1050-evk/imxrt1050-evk.c | 94 ++++++
configs/imxrt1050-evk_defconfig | 52 ++++
include/configs/imxrt1050-evk.h | 68 +++++
include/dt-bindings/clock/imxrt-clock.h | 272 ++++++++++++++++++
11 files changed, 727 insertions(+)
create mode 100644 arch/arm/dts/imxrt1050-evk.dts
create mode 100644 arch/arm/dts/imxrt1050.dtsi
create mode 100644 board/freescale/imxrt1050-evk/Kconfig
create mode 100644 board/freescale/imxrt1050-evk/MAINTAINERS
create mode 100644 board/freescale/imxrt1050-evk/Makefile
create mode 100644 board/freescale/imxrt1050-evk/imxrt1050-evk.c
create mode 100644 configs/imxrt1050-evk_defconfig
create mode 100644 include/configs/imxrt1050-evk.h
create mode 100644 include/dt-bindings/clock/imxrt-clock.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 62da168ef8..5ac490fa5e 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -631,6 +631,8 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
+dtb-$(CONFIG_ARCH_IMXRT) += imxrt1050-evk.dtb
+
dtb-$(CONFIG_RCAR_GEN2) += \
r8a7790-lager-u-boot.dtb \
r8a7790-stout-u-boot.dtb \
diff --git a/arch/arm/dts/imxrt1050-evk.dts b/arch/arm/dts/imxrt1050-evk.dts
new file mode 100644
index 0000000000..8b5ec7fe9f
--- /dev/null
+++ b/arch/arm/dts/imxrt1050-evk.dts
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.bene...@benettiengineering.com>
+ */
+
+/dts-v1/;
+#include "imxrt1050.dtsi"
+#include <dt-bindings/pinctrl/pins-imxrt1050.h>
+
+/ {
+ model = "NXP IMXRT1050-evk board";
+ compatible = "fsl,imxrt1050-evk", "fsl,imxrt1050";
+
+ chosen {
+ u-boot,dm-spl;
+ bootargs = "root=/dev/ram";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ reg = <0x80000000 0x2000000>;
+ };
+
+ aliases {
+ serial0 = &lpuart1;
+ };
+};
+
+&lpuart1 { /* console */
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+ status = "okay";
+};
+
+&semc {
+ /*
+ * Memory configuration from sdram datasheet IS42S32800G-6BLI
+ */
+ fsl,sdram-mux = /bits/ 8 <MUX_A8_SDRAM_A8
+ MUX_CSX0_SDRAM_CS1
+ 0
+ 0
+ 0
+ 0>;
+ fsl,sdram-control = /bits/ 8 <MEM_WIDTH_16BITS
+ BL_8
+ COL_9BITS
+ CL_3>;
+ fsl,sdram-timing = /bits/ 8 <TRP_3
+ TRCD_3
+ TRFC_10
+ TWR_3>;
+
+ bank1: bank@0 {
+ u-boot,dm-spl;
+ fsl,base-address = <0x80000000>;
+ fsl,memory-size = <MEM_SIZE_32M>;
+ };
+};
+
+&iomuxc {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart1>;
+
+ imxrt1050-evk {
+ u-boot,dm-spl;
+ pinctrl_lpuart1: lpuart1grp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_AD_B0_12_LPUART1_TXD
0xf1
+ MXRT1050_IOMUXC_GPIO_AD_B0_13_LPUART1_RXD
0xf1
+ >;
+ };
+
+ pinctrl_semc: semcgrp {
+ u-boot,dm-spl;
+ fsl,pins = <
+ MXRT1050_IOMUXC_GPIO_EMC_00_SEMC_DA00
0xf1 /* SEMC_D0 */
+ MXRT1050_IOMUXC_GPIO_EMC_01_SEMC_DA01
0xf1 /* SEMC_D1 */
+ MXRT1050_IOMUXC_GPIO_EMC_02_SEMC_DA02
0xf1 /* SEMC_D2 */
+ MXRT1050_IOMUXC_GPIO_EMC_03_SEMC_DA03
0xf1 /* SEMC_D3 */
+ MXRT1050_IOMUXC_GPIO_EMC_04_SEMC_DA04
0xf1 /* SEMC_D4 */
+ MXRT1050_IOMUXC_GPIO_EMC_05_SEMC_DA05
0xf1 /* SEMC_D5 */
+ MXRT1050_IOMUXC_GPIO_EMC_06_SEMC_DA06
0xf1 /* SEMC_D6 */
+ MXRT1050_IOMUXC_GPIO_EMC_07_SEMC_DA07
0xf1 /* SEMC_D7 */
+ MXRT1050_IOMUXC_GPIO_EMC_08_SEMC_DM00
0xf1 /* SEMC_DM0 */
+ MXRT1050_IOMUXC_GPIO_EMC_09_SEMC_ADDR00
0xf1 /* SEMC_A0 */
+ MXRT1050_IOMUXC_GPIO_EMC_10_SEMC_ADDR01
0xf1 /* SEMC_A1 */
+ MXRT1050_IOMUXC_GPIO_EMC_11_SEMC_ADDR02
0xf1 /* SEMC_A2 */
+ MXRT1050_IOMUXC_GPIO_EMC_12_SEMC_ADDR03
0xf1 /* SEMC_A3 */
+ MXRT1050_IOMUXC_GPIO_EMC_13_SEMC_ADDR04
0xf1 /* SEMC_A4 */
+ MXRT1050_IOMUXC_GPIO_EMC_14_SEMC_ADDR05
0xf1 /* SEMC_A5 */
+ MXRT1050_IOMUXC_GPIO_EMC_15_SEMC_ADDR06
0xf1 /* SEMC_A6 */
+ MXRT1050_IOMUXC_GPIO_EMC_16_SEMC_ADDR07
0xf1 /* SEMC_A7 */
+ MXRT1050_IOMUXC_GPIO_EMC_17_SEMC_ADDR08
0xf1 /* SEMC_A8 */
+ MXRT1050_IOMUXC_GPIO_EMC_18_SEMC_ADDR09
0xf1 /* SEMC_A9 */
+ MXRT1050_IOMUXC_GPIO_EMC_19_SEMC_ADDR11
0xf1 /* SEMC_A11 */
+ MXRT1050_IOMUXC_GPIO_EMC_20_SEMC_ADDR12
0xf1 /* SEMC_A12 */
+ MXRT1050_IOMUXC_GPIO_EMC_21_SEMC_BA0
0xf1 /* SEMC_BA0 */
+ MXRT1050_IOMUXC_GPIO_EMC_22_SEMC_BA1
0xf1 /* SEMC_BA1 */
+ MXRT1050_IOMUXC_GPIO_EMC_23_SEMC_ADDR10
0xf1 /* SEMC_A10 */
+ MXRT1050_IOMUXC_GPIO_EMC_24_SEMC_CAS
0xf1 /* SEMC_CAS */
+ MXRT1050_IOMUXC_GPIO_EMC_25_SEMC_RAS
0xf1 /* SEMC_RAS */
+ MXRT1050_IOMUXC_GPIO_EMC_26_SEMC_CLK
0xf1 /* SEMC_CLK */
+ MXRT1050_IOMUXC_GPIO_EMC_27_SEMC_CKE
0xf1 /* SEMC_CKE */
+ MXRT1050_IOMUXC_GPIO_EMC_28_SEMC_WE
0xf1 /* SEMC_WE */
+ MXRT1050_IOMUXC_GPIO_EMC_29_SEMC_CS0
0xf1 /* SEMC_CS0 */
+ MXRT1050_IOMUXC_GPIO_EMC_30_SEMC_DA08
0xf1 /* SEMC_D8 */
+ MXRT1050_IOMUXC_GPIO_EMC_31_SEMC_DA09
0xf1 /* SEMC_D9 */
+ MXRT1050_IOMUXC_GPIO_EMC_32_SEMC_DA10
0xf1 /* SEMC_D10 */
+ MXRT1050_IOMUXC_GPIO_EMC_33_SEMC_DA11
0xf1 /* SEMC_D11 */
+ MXRT1050_IOMUXC_GPIO_EMC_34_SEMC_DA12
0xf1 /* SEMC_D12 */
+ MXRT1050_IOMUXC_GPIO_EMC_35_SEMC_DA13
0xf1 /* SEMC_D13 */
+ MXRT1050_IOMUXC_GPIO_EMC_36_SEMC_DA14
0xf1 /* SEMC_D14 */
+ MXRT1050_IOMUXC_GPIO_EMC_37_SEMC_DA15
0xf1 /* SEMC_D15 */
+ MXRT1050_IOMUXC_GPIO_EMC_38_SEMC_DM01
0xf1 /* SEMC_DM1 */
+ MXRT1050_IOMUXC_GPIO_EMC_39_SEMC_DQS
(IMX_PAD_SION | 0xf1) /* SEMC_DQS */
+ >;
+ };
+ };
+};
diff --git a/arch/arm/dts/imxrt1050.dtsi b/arch/arm/dts/imxrt1050.dtsi
new file mode 100644
index 0000000000..a6416477f5
--- /dev/null
+++ b/arch/arm/dts/imxrt1050.dtsi
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.bene...@benettiengineering.com>
+ */
+
+#include "skeleton.dtsi"
+#include "armv7-m.dtsi"
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/imxrt-clock.h>
+#include <dt-bindings/memory/imxrt-sdram.h>
+
+/ {
+ clocks {
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ };
+
+ ckih1 {
+ compatible = "fsl,imx-ckih1", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ u-boot,dm-spl;
+
+ semc: semc@402f0000 {
+ u-boot,dm-spl;
+ compatible = "fsl,imxrt-semc";
+ reg = <0x402f0000 0x4000>;
+ /*clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;*/
+ pinctrl-0 = <&pinctrl_semc>;
+ pinctrl-names = "default";
+ status = "okay";
+ };
+
+ lpuart1: serial@40184000 {
+ compatible = "fsl,imxrt-lpuart";
+ reg = <0x40184000 0x4000>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMXRT_CLK_UART_SERIAL>,
+ <&clks IMXRT_CLK_UART_IPG>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clks IMXRT_CLK_UART_SERIAL>;
+ assigned-clock-rates = <80000000>;
+ status = "disabled";
+ };
+
+ iomuxc: iomuxc@401f8000 {
+ compatible = "fsl,imxrt-iomuxc";
+ reg = <0x401f8000 0x4000>;
+ fsl,mux_mask = <0x7>;
+ };
+
+ clks: ccm@400fc000 {
+ compatible = "fsl,imxrt-ccm";
+ reg = <0x400fc000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ #clock-cells = <1>;
+ };
+ };
+};
diff --git a/arch/arm/mach-imx/imxrt/Kconfig b/arch/arm/mach-imx/imxrt/Kconfig
index 1da002336b..45dd8fcd76 100644
--- a/arch/arm/mach-imx/imxrt/Kconfig
+++ b/arch/arm/mach-imx/imxrt/Kconfig
@@ -3,4 +3,15 @@ if ARCH_IMXRT
config SYS_SOC
default "imxrt"
+choice
+ prompt "IMXRT board select"
+ optional
+
+config TARGET_IMXRT1050_EVK
+ bool "Support imxrt1050 EVK board"
+
+endchoice
+
+source "board/freescale/imxrt1050-evk/Kconfig"
+
endif
diff --git a/board/freescale/imxrt1050-evk/Kconfig
b/board/freescale/imxrt1050-evk/Kconfig
new file mode 100644
index 0000000000..0c07c0c5e0
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/Kconfig
@@ -0,0 +1,19 @@
+if TARGET_IMXRT1050_EVK
+
+config SYS_BOARD
+ string
+ default "imxrt1050-evk"
+
+config SYS_VENDOR
+ string
+ default "freescale"
+
+config SYS_SOC
+ string
+ default "imxrt"
+
+config SYS_CONFIG_NAME
+ string
+ default "imxrt1050-evk"
+
+endif
diff --git a/board/freescale/imxrt1050-evk/MAINTAINERS
b/board/freescale/imxrt1050-evk/MAINTAINERS
new file mode 100644
index 0000000000..a872855452
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/MAINTAINERS
@@ -0,0 +1,6 @@
+IMXRT1050 EVALUATION KIT
+M: Giulio Benetti <giulio.bene...@benettiengineering.com>
+S: Maintained
+F: board/freescale/imxrt1050-evk
+F: include/configs/imxrt1050-evk.h
+F: configs/imxrt1050-evk_defconfig
diff --git a/board/freescale/imxrt1050-evk/Makefile
b/board/freescale/imxrt1050-evk/Makefile
new file mode 100644
index 0000000000..0e984d1d7a
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2019
+# Author(s): Giulio Benetti <giulio.bene...@benettiengineering.com>
+
+obj-y := imxrt1050-evk.o
diff --git a/board/freescale/imxrt1050-evk/imxrt1050-evk.c
b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
new file mode 100644
index 0000000000..94fddbbc2f
--- /dev/null
+++ b/board/freescale/imxrt1050-evk/imxrt1050-evk.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.bene...@benettiengineering.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+#ifndef CONFIG_SUPPORT_SPL
+ int rv;
+ struct udevice *dev;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv) {
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+ }
+
+#endif
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+#ifdef CONFIG_SPL_BUILD
+#ifdef CONFIG_SPL_OS_BOOT
+int spl_start_uboot(void)
+{
+ debug("SPL: booting kernel\n");
+ /* break into full u-boot on 'c' */
+ return serial_tstc() && serial_getc() == 'c';
+}
+#endif
+
+int spl_dram_init(void)
+{
+ struct udevice *dev;
+ int rv;
+
+ rv = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (rv)
+ debug("DRAM init failed: %d\n", rv);
+ return rv;
+}
+
+void spl_board_init(void)
+{
+ spl_dram_init();
+ preloader_console_init();
+ arch_cpu_init(); /* to configure mpu for sdram rw permissions */
+}
+
+u32 spl_boot_device(void)
+{
+ return BOOT_DEVICE_XIP;
+}
+
+u32 get_lpuart_clk(void)
+{
+ /* On startup lpuart is clocked by bypassed PLL3(OSC) that is
+ * 24Mhz, and its clock source is divided by 6 as referenced in RM
+ */
+ return 4000000;
+}
+#endif
+
+u32 get_board_rev(void)
+{
+ return 0;
+}
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
diff --git a/configs/imxrt1050-evk_defconfig b/configs/imxrt1050-evk_defconfig
new file mode 100644
index 0000000000..355f0f6250
--- /dev/null
+++ b/configs/imxrt1050-evk_defconfig
@@ -0,0 +1,52 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMXRT=y
+CONFIG_SYS_TEXT_BASE=0x80000000
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_TARGET_IMXRT1050_EVK=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_SPL_TEXT_BASE=0x20200000
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_BOOTCOMMAND is not set
+CONFIG_CONSOLE_MUX=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SYS_MALLOC_SIMPLE=y
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_BOOTM_NETBSD is not set
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+# CONFIG_CMD_NVEDIT_EFI is not set
+# CONFIG_CMD_MII is not set
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="imxrt1050-evk"
+CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent interrupts"
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_OF_TRANSLATE is not set
+# CONFIG_INPUT is not set
+CONFIG_DM_MMC=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMXRT=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_IMXRT_SDRAM=y
+CONFIG_FSL_LPUART=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_HEXDUMP=y
+# CONFIG_GENERATE_SMBIOS_TABLE is not set
diff --git a/include/configs/imxrt1050-evk.h b/include/configs/imxrt1050-evk.h
new file mode 100644
index 0000000000..4627a7b06e
--- /dev/null
+++ b/include/configs/imxrt1050-evk.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019
+ * Author(s): Giulio Benetti <giulio.bene...@benettiengineering.com>
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x20280000
+
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SYS_LOAD_ADDR 0x20200000
+#else
+#define CONFIG_SYS_LOAD_ADDR 0x80000000
+#define CONFIG_LOADADDR 0x80000000
+#endif
+
+/*
+ * Configuration of the external SDRAM memory
+ */
+#define CONFIG_ENV_SIZE (8 << 10)
+
+#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer is clocked at
24MHz */
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+#define CONFIG_SYS_CBSIZE 1024
+
+#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
+
+#define BOOT_TARGET_DEVICES(func) \
+ func(MMC, mmc, 0)
+
+/*
+ * Command line configuration.
+ */
+#define CONFIG_BOARD_LATE_INIT
+
+/* For SPL */
+#ifdef CONFIG_SUPPORT_SPL
+#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
+#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
+#define CONFIG_SYS_SPL_LEN 0x00008000
+#define CONFIG_SYS_UBOOT_START 0x080083FD
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_SPL_LEN)
+
+/* DT blob (fdt) address */
+#define CONFIG_SYS_FDT_BASE (CONFIG_SYS_FLASH_BASE + \
+ 0x1C0000)
+#endif
+/* For SPL ends */
+
+/* For splashcreen */
+#ifdef CONFIG_DM_VIDEO
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_BMP_16BPP
+#define CONFIG_BMP_24BPP
+#define CONFIG_BMP_32BPP
+#define CONFIG_SPLASH_SCREEN
+#define CONFIG_SPLASH_SCREEN_ALIGN
+#endif
+
+#endif /* __CONFIG_H */
diff --git a/include/dt-bindings/clock/imxrt-clock.h
b/include/dt-bindings/clock/imxrt-clock.h
new file mode 100644
index 0000000000..2eb9eb8a67
--- /dev/null
+++ b/include/dt-bindings/clock/imxrt-clock.h
@@ -0,0 +1,272 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright(C) 2019
+ * Author(s): Giulio Benetti <giulio.bene...@benettiengineering.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_IMXRT_H
+#define __DT_BINDINGS_CLOCK_IMXRT_H
+
+#define IMXRT_CLK_DUMMY 0
+#define IMXRT_CLK_CKIL 1
+#define IMXRT_CLK_CKIH 2
+#define IMXRT_CLK_OSC 3
+#define IMXRT_CLK_PLL2_PFD0_352M 4
+#define IMXRT_CLK_PLL2_PFD1_594M 5
+#define IMXRT_CLK_PLL2_PFD2_396M 6
+#define IMXRT_CLK_PLL3_PFD0_720M 7
+#define IMXRT_CLK_PLL3_PFD1_540M 8
+#define IMXRT_CLK_PLL3_PFD2_508M 9
+#define IMXRT_CLK_PLL3_PFD3_454M 10
+#define IMXRT_CLK_PLL2_198M 11
+#define IMXRT_CLK_PLL3_120M 12
+#define IMXRT_CLK_PLL3_80M 13
+#define IMXRT_CLK_PLL3_60M 14
+#define IMXRT_CLK_TWD 15
+#define IMXRT_CLK_STEP 16
+#define IMXRT_CLK_PLL1_SW 17
+#define IMXRT_CLK_PERIPH_PRE 18
+#define IMXRT_CLK_PERIPH2_PRE 19
+#define IMXRT_CLK_PERIPH_CLK2_SEL 20
+#define IMXRT_CLK_PERIPH2_CLK2_SEL 21
+#define IMXRT_CLK_AXI_SEL 22
+#define IMXRT_CLK_ESAI_SEL 23
+#define IMXRT_CLK_ASRC_SEL 24
+#define IMXRT_CLK_SPDIF_SEL 25
+#define IMXRT_CLK_GPU2D_AXI 26
+#define IMXRT_CLK_GPU3D_AXI 27
+#define IMXRT_CLK_GPU2D_CORE_SEL 28
+#define IMXRT_CLK_GPU3D_CORE_SEL 29
+#define IMXRT_CLK_GPU3D_SHADER_SEL 30
+#define IMXRT_CLK_IPU1_SEL 31
+#define IMXRT_CLK_IPU2_SEL 32
+#define IMXRT_CLK_LDB_DI0_SEL 33
+#define IMXRT_CLK_LDB_DI1_SEL 34
+#define IMXRT_CLK_IPU1_DI0_PRE_SEL 35
+#define IMXRT_CLK_IPU1_DI1_PRE_SEL 36
+#define IMXRT_CLK_IPU2_DI0_PRE_SEL 37
+#define IMXRT_CLK_IPU2_DI1_PRE_SEL 38
+#define IMXRT_CLK_IPU1_DI0_SEL 39
+#define IMXRT_CLK_IPU1_DI1_SEL 40
+#define IMXRT_CLK_IPU2_DI0_SEL 41
+#define IMXRT_CLK_IPU2_DI1_SEL 42
+#define IMXRT_CLK_HSI_TX_SEL 43
+#define IMXRT_CLK_PCIE_AXI_SEL 44
+#define IMXRT_CLK_SSI1_SEL 45
+#define IMXRT_CLK_SSI2_SEL 46
+#define IMXRT_CLK_SSI3_SEL 47
+#define IMXRT_CLK_USDHC1_SEL 48
+#define IMXRT_CLK_USDHC2_SEL 49
+#define IMXRT_CLK_USDHC3_SEL 50
+#define IMXRT_CLK_USDHC4_SEL 51
+#define IMXRT_CLK_ENFC_SEL 52
+#define IMXRT_CLK_EIM_SEL 53
+#define IMXRT_CLK_EIM_SLOW_SEL 54
+#define IMXRT_CLK_VDO_AXI_SEL 55
+#define IMXRT_CLK_VPU_AXI_SEL 56
+#define IMXRT_CLK_CKO1_SEL 57
+#define IMXRT_CLK_PERIPH 58
+#define IMXRT_CLK_PERIPH2 59
+#define IMXRT_CLK_PERIPH_CLK2 60
+#define IMXRT_CLK_PERIPH2_CLK2 61
+#define IMXRT_CLK_IPG 62
+#define IMXRT_CLK_IPG_PER 63
+#define IMXRT_CLK_ESAI_PRED 64
+#define IMXRT_CLK_ESAI_PODF 65
+#define IMXRT_CLK_ASRC_PRED 66
+#define IMXRT_CLK_ASRC_PODF 67
+#define IMXRT_CLK_SPDIF_PRED 68
+#define IMXRT_CLK_SPDIF_PODF 69
+#define IMXRT_CLK_CAN_ROOT 70
+#define IMXRT_CLK_ECSPI_ROOT 71
+#define IMXRT_CLK_GPU2D_CORE_PODF 72
+#define IMXRT_CLK_GPU3D_CORE_PODF 73
+#define IMXRT_CLK_GPU3D_SHADER 74
+#define IMXRT_CLK_IPU1_PODF 75
+#define IMXRT_CLK_IPU2_PODF 76
+#define IMXRT_CLK_LDB_DI0_PODF 77
+#define IMXRT_CLK_LDB_DI1_PODF 78
+#define IMXRT_CLK_IPU1_DI0_PRE 79
+#define IMXRT_CLK_IPU1_DI1_PRE 80
+#define IMXRT_CLK_IPU2_DI0_PRE 81
+#define IMXRT_CLK_IPU2_DI1_PRE 82
+#define IMXRT_CLK_HSI_TX_PODF 83
+#define IMXRT_CLK_SSI1_PRED 84
+#define IMXRT_CLK_SSI1_PODF 85
+#define IMXRT_CLK_SSI2_PRED 86
+#define IMXRT_CLK_SSI2_PODF 87
+#define IMXRT_CLK_SSI3_PRED 88
+#define IMXRT_CLK_SSI3_PODF 89
+#define IMXRT_CLK_UART_SERIAL_PODF 90
+#define IMXRT_CLK_USDHC1_PODF 91
+#define IMXRT_CLK_USDHC2_PODF 92
+#define IMXRT_CLK_USDHC3_PODF 93
+#define IMXRT_CLK_USDHC4_PODF 94
+#define IMXRT_CLK_ENFC_PRED 95
+#define IMXRT_CLK_ENFC_PODF 96
+#define IMXRT_CLK_EIM_PODF 97
+#define IMXRT_CLK_EIM_SLOW_PODF 98
+#define IMXRT_CLK_VPU_AXI_PODF 99
+#define IMXRT_CLK_CKO1_PODF 100
+#define IMXRT_CLK_AXI 101
+#define IMXRT_CLK_MMDC_CH0_AXI_PODF 102
+#define IMXRT_CLK_MMDC_CH1_AXI_PODF 103
+#define IMXRT_CLK_ARM 104
+#define IMXRT_CLK_AHB 105
+#define IMXRT_CLK_APBH_DMA 106
+#define IMXRT_CLK_ASRC 107
+#define IMXRT_CLK_CAN1_IPG 108
+#define IMXRT_CLK_CAN1_SERIAL 109
+#define IMXRT_CLK_CAN2_IPG 110
+#define IMXRT_CLK_CAN2_SERIAL 111
+#define IMXRT_CLK_ECSPI1 112
+#define IMXRT_CLK_ECSPI2 113
+#define IMXRT_CLK_ECSPI3 114
+#define IMXRT_CLK_ECSPI4 115
+#define IMX6Q_CLK_ECSPI5 116
+#define IMX6DL_CLK_I2C4 116
+#define IMXRT_CLK_ENET 117
+#define IMXRT_CLK_ESAI_EXTAL 118
+#define IMXRT_CLK_GPT_IPG 119
+#define IMXRT_CLK_GPT_IPG_PER 120
+#define IMXRT_CLK_GPU2D_CORE 121
+#define IMXRT_CLK_GPU3D_CORE 122
+#define IMXRT_CLK_HDMI_IAHB 123
+#define IMXRT_CLK_HDMI_ISFR 124
+#define IMXRT_CLK_I2C1 125
+#define IMXRT_CLK_I2C2 126
+#define IMXRT_CLK_I2C3 127
+#define IMXRT_CLK_IIM 128
+#define IMXRT_CLK_ENFC 129
+#define IMXRT_CLK_IPU1 130
+#define IMXRT_CLK_IPU1_DI0 131
+#define IMXRT_CLK_IPU1_DI1 132
+#define IMXRT_CLK_IPU2 133
+#define IMXRT_CLK_IPU2_DI0 134
+#define IMXRT_CLK_LDB_DI0 135
+#define IMXRT_CLK_LDB_DI1 136
+#define IMXRT_CLK_IPU2_DI1 137
+#define IMXRT_CLK_HSI_TX 138
+#define IMXRT_CLK_MLB 139
+#define IMXRT_CLK_MMDC_CH0_AXI 140
+#define IMXRT_CLK_MMDC_CH1_AXI 141
+#define IMXRT_CLK_OCRAM 142
+#define IMXRT_CLK_OPENVG_AXI 143
+#define IMXRT_CLK_PCIE_AXI 144
+#define IMXRT_CLK_PWM1 145
+#define IMXRT_CLK_PWM2 146
+#define IMXRT_CLK_PWM3 147
+#define IMXRT_CLK_PWM4 148
+#define IMXRT_CLK_PER1_BCH 149
+#define IMXRT_CLK_GPMI_BCH_APB 150
+#define IMXRT_CLK_GPMI_BCH 151
+#define IMXRT_CLK_GPMI_IO 152
+#define IMXRT_CLK_GPMI_APB 153
+#define IMXRT_CLK_SATA 154
+#define IMXRT_CLK_SDMA 155
+#define IMXRT_CLK_SPBA 156
+#define IMXRT_CLK_SSI1 157
+#define IMXRT_CLK_SSI2 158
+#define IMXRT_CLK_SSI3 159
+#define IMXRT_CLK_UART_IPG 160
+#define IMXRT_CLK_UART_SERIAL 161
+#define IMXRT_CLK_USBOH3 162
+#define IMXRT_CLK_USDHC1 163
+#define IMXRT_CLK_USDHC2 164
+#define IMXRT_CLK_USDHC3 165
+#define IMXRT_CLK_USDHC4 166
+#define IMXRT_CLK_VDO_AXI 167
+#define IMXRT_CLK_VPU_AXI 168
+#define IMXRT_CLK_CKO1 169
+#define IMXRT_CLK_PLL1_SYS 170
+#define IMXRT_CLK_PLL2_BUS 171
+#define IMXRT_CLK_PLL3_USB_OTG 172
+#define IMXRT_CLK_PLL4_AUDIO 173
+#define IMXRT_CLK_PLL5_VIDEO 174
+#define IMXRT_CLK_PLL8_MLB 175
+#define IMXRT_CLK_PLL7_USB_HOST 176
+#define IMXRT_CLK_PLL6_ENET 177
+#define IMXRT_CLK_SSI1_IPG 178
+#define IMXRT_CLK_SSI2_IPG 179
+#define IMXRT_CLK_SSI3_IPG 180
+#define IMXRT_CLK_ROM 181
+#define IMXRT_CLK_USBPHY1 182
+#define IMXRT_CLK_USBPHY2 183
+#define IMXRT_CLK_LDB_DI0_DIV_3_5 184
+#define IMXRT_CLK_LDB_DI1_DIV_3_5 185
+#define IMXRT_CLK_SATA_REF 186
+#define IMXRT_CLK_SATA_REF_100M 187
+#define IMXRT_CLK_PCIE_REF 188
+#define IMXRT_CLK_PCIE_REF_125M 189
+#define IMXRT_CLK_ENET_REF 190
+#define IMXRT_CLK_USBPHY1_GATE 191
+#define IMXRT_CLK_USBPHY2_GATE 192
+#define IMXRT_CLK_PLL4_POST_DIV 193
+#define IMXRT_CLK_PLL5_POST_DIV 194
+#define IMXRT_CLK_PLL5_VIDEO_DIV 195
+#define IMXRT_CLK_EIM_SLOW 196
+#define IMXRT_CLK_SPDIF 197
+#define IMXRT_CLK_CKO2_SEL 198
+#define IMXRT_CLK_CKO2_PODF 199
+#define IMXRT_CLK_CKO2 200
+#define IMXRT_CLK_CKO 201
+#define IMXRT_CLK_VDOA 202
+#define IMXRT_CLK_PLL4_AUDIO_DIV 203
+#define IMXRT_CLK_LVDS1_SEL 204
+#define IMXRT_CLK_LVDS2_SEL 205
+#define IMXRT_CLK_LVDS1_GATE 206
+#define IMXRT_CLK_LVDS2_GATE 207
+#define IMXRT_CLK_ESAI_IPG 208
+#define IMXRT_CLK_ESAI_MEM 209
+#define IMXRT_CLK_ASRC_IPG 210
+#define IMXRT_CLK_ASRC_MEM 211
+#define IMXRT_CLK_LVDS1_IN 212
+#define IMXRT_CLK_LVDS2_IN 213
+#define IMXRT_CLK_ANACLK1 214
+#define IMXRT_CLK_ANACLK2 215
+#define IMXRT_PLL1_BYPASS_SRC 216
+#define IMXRT_PLL2_BYPASS_SRC 217
+#define IMXRT_PLL3_BYPASS_SRC 218
+#define IMXRT_PLL4_BYPASS_SRC 219
+#define IMXRT_PLL5_BYPASS_SRC 220
+#define IMXRT_PLL6_BYPASS_SRC 221
+#define IMXRT_PLL7_BYPASS_SRC 222
+#define IMXRT_CLK_PLL1 223
+#define IMXRT_CLK_PLL2 224
+#define IMXRT_CLK_PLL3 225
+#define IMXRT_CLK_PLL4 226
+#define IMXRT_CLK_PLL5 227
+#define IMXRT_CLK_PLL6 228
+#define IMXRT_CLK_PLL7 229
+#define IMXRT_PLL1_BYPASS 230
+#define IMXRT_PLL2_BYPASS 231
+#define IMXRT_PLL3_BYPASS 232
+#define IMXRT_PLL4_BYPASS 233
+#define IMXRT_PLL5_BYPASS 234
+#define IMXRT_PLL6_BYPASS 235
+#define IMXRT_PLL7_BYPASS 236
+#define IMXRT_CLK_GPT_3M 237
+#define IMXRT_CLK_VIDEO_27M 238
+#define IMXRT_CLK_MIPI_CORE_CFG 239
+#define IMXRT_CLK_MIPI_IPG 240
+#define IMXRT_CLK_CAAM_MEM 241
+#define IMXRT_CLK_CAAM_ACLK 242
+#define IMXRT_CLK_CAAM_IPG 243
+#define IMXRT_CLK_SPDIF_GCLK 244
+#define IMXRT_CLK_UART_SEL 245
+#define IMXRT_CLK_IPG_PER_SEL 246
+#define IMXRT_CLK_ECSPI_SEL 247
+#define IMXRT_CLK_CAN_SEL 248
+#define IMXRT_CLK_MMDC_CH1_AXI_CG 249
+#define IMXRT_CLK_PRE0 250
+#define IMXRT_CLK_PRE1 251
+#define IMXRT_CLK_PRE2 252
+#define IMXRT_CLK_PRE3 253
+#define IMXRT_CLK_PRG0_AXI 254
+#define IMXRT_CLK_PRG1_AXI 255
+#define IMXRT_CLK_PRG0_APB 256
+#define IMXRT_CLK_PRG1_APB 257
+#define IMXRT_CLK_PRE_AXI 258
+#define IMXRT_CLK_END 259
+
+#endif /* __DT_BINDINGS_CLOCK_IMXRT_H */
--
2.20.1
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