Hi folks,
I am trying to get a recent U-Boot working on my DNS323 (B1). Building
on the work of Albert Aribaud, I have been able to get it to boot
successfully from the existing U-Boot boot loader having defined
CONFIG_SKIP_LOWLEVEL_INIT, and (with a tweak to the
ORION5X_DEFADR_BOOTROM and ORION5X_DEFSZ_BOOTROM defines to match my
flash base address and size) have been able to trigger the flash to
enter the CFI QRY mode.
However, the standard flash_detect_cfi routine in
drivers/mtd/cfi_flash.c is unable to detect my flash.
This is what I am currently able to do:
DNS323B1> mw.b 0xff8000aa 0x98
DNS323B1> md.b 0xff800020 0x40
ff800020: 51 51 52 52 59 59 02 02 00 00 40 40 00 00 00 00
QQRRYY....@@....
ff800030: 00 00 00 00 00 00 27 27 36 36 00 00 00 00 04 04
......''66......
ff800040: 00 00 0a 0a 00 00 05 05 00 00 04 04 00 00 17 17
................
ff800050: 02 02 00 00 00 00 00 00 02 02 07 07 00 00 20 20
..............
As you can see, the QRY response which is supposed to be at 0x20-0x22 is
actually duplicated as QQRRYY at 0x20-0x25.
The flash part is a 8 MB Spansion S29GL064M90TFIR4, and the data sheet
can be found at:
http://www.spansion.com/Support/Datasheets/s29gl-m_00_b8_e.pdf
Here is the output of a boot run, with DEBUG defined in flash.c:
-----x8-----x8-----
Starting kernel ...
U-Boot 2010.06-00074-gc63cbcc-dirty (Jul 10 2010 - 13:04:52)DNS323_B1
SoC: Orion5x MV88F5182-A2
DRAM: 64 MiB
flash detect cfi
fwc addr ff800000 cmd f0 f0f0 16bit x 8 bit
fwc addr ff800000 cmd ff ffff 16bit x 8 bit
fwc addr ff8000aa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= ffff 5151
fwc addr ff800aaa cmd 98 9898 16bit x 8 bit
is= cmd 51(Q) addr ff800020 is= ffff 5151
fwc addr ff800000 cmd f0 00f0 16bit x 16 bit
fwc addr ff800000 cmd ff 00ff 16bit x 16 bit
fwc addr ff8000aa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= ffff 0051
fwc addr ff800aaa cmd 98 0098 16bit x 16 bit
is= cmd 51(Q) addr ff800020 is= ffff 0051
fwc addr ff800000 cmd f0 f0f0f0f0 32bit x 8 bit
fwc addr ff800000 cmd ff ffffffff 32bit x 8 bit
fwc addr ff800154 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 51515151
fwc addr ff801554 cmd 98 98989898 32bit x 8 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 51515151
fwc addr ff800000 cmd f0 00f000f0 32bit x 16 bit
fwc addr ff800000 cmd ff 00ff00ff 32bit x 16 bit
fwc addr ff800154 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00510051
fwc addr ff801554 cmd 98 00980098 32bit x 16 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00510051
fwc addr ff800000 cmd f0 000000f0 32bit x 32 bit
fwc addr ff800000 cmd ff 000000ff 32bit x 32 bit
fwc addr ff800154 cmd 98 00000098 32bit x 32 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00000051
fwc addr ff801554 cmd 98 00000098 32bit x 32 bit
is= cmd 51(Q) addr ff800040 is= ffffffff 00000051
fwrite addr ff800000 cmd f0 f0f0f0f0f0f0f0f0 64 bit x 8 bit
fwrite addr ff800000 cmd ff ffffffffffffffff 64 bit x 8 bit
fwrite addr ff8002a8 cmd 98 9898989898989898 64 bit x 8 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5151515151515151
fwrite addr ff802aa8 cmd 98 9898989898989898 64 bit x 8 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5151515151515151
fwrite addr ff800000 cmd f0 f000f000f000f000 64 bit x 16 bit
fwrite addr ff800000 cmd ff ff00ff00ff00ff00 64 bit x 16 bit
fwrite addr ff8002a8 cmd 98 9800980098009800 64 bit x 16 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5100510051005100
fwrite addr ff802aa8 cmd 98 9800980098009800 64 bit x 16 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5100510051005100
fwrite addr ff800000 cmd f0 f0000000f0000000 64 bit x 32 bit
fwrite addr ff800000 cmd ff ff000000ff000000 64 bit x 32 bit
fwrite addr ff8002a8 cmd 98 9800000098000000 64 bit x 32 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5100000051000000
fwrite addr ff802aa8 cmd 98 9800000098000000 64 bit x 32 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5100000051000000
fwrite addr ff800000 cmd f0 f000000000000000 64 bit x 64 bit
fwrite addr ff800000 cmd ff ff00000000000000 64 bit x 64 bit
fwrite addr ff8002a8 cmd 98 9800000000000000 64 bit x 64 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5100000000000000
fwrite addr ff802aa8 cmd 98 9800000000000000 64 bit x 64 bit
is= cmd 51(Q) addr ff800080 is= ffffffffffffffff 5100000000000000
not found
## Unknown FLASH on Bank 1 (ff800000) - Size = 0x00000000 = 0 MB
Flash: 0 Bytes
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
DNS323B1>
-----x8-----x8-----
I have tried defining the flash as a 16-bit part with:
#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
(which was used to generate the above bootlog), as well as 8-bit
(omitting that define), and neither is able to detect the flash part.
It seems that it is a mixed 8/16 bit device, and the current u-boot code
does not support that very well. Either that, or I have not found the
right defines.
If anyone has any ideas of what I am doing wrong, or what I should do to
debug this further, please do let me know.
My current diff against mainline u-boot is included as an attachment (I
know, sorry, but Thunderbird tends to mangle inline patches). Please
ignore board_flash_get_legacy in board/Marvell/dns323_b1/dns323_b1.c, I
do not define CONFIG_FLASH_CFI_LEGACY. This is just in case there is no
alternative solution via the standard CFI routines, and is a pure copy
and paste from the edminiv2 code.
Regards,
Rogan
diff --git a/arch/arm/include/asm/arch-orion5x/cpu.h
b/arch/arm/include/asm/arch-orion5x/cpu.h
index 22e2dd3..fc7fa7c 100644
--- a/arch/arm/include/asm/arch-orion5x/cpu.h
+++ b/arch/arm/include/asm/arch-orion5x/cpu.h
@@ -102,8 +102,10 @@ enum orion5x_cpu_attrib {
#define ORION5X_DEFADR_DEV_CS2 0xfa800000
#define ORION5X_DEFSZ_DEV_CS2 (1*1024*1024)
+#ifndef ORION5X_DEFADR_BOOTROM
#define ORION5X_DEFADR_BOOTROM 0xFFF80000
#define ORION5X_DEFSZ_BOOTROM (512*1024)
+#endif
/*
* PCIE registers are used for SoC device ID and revision
diff --git a/board/Marvell/dns323_b1/Makefile b/board/Marvell/dns323_b1/Makefile
new file mode 100644
index 0000000..fae0330
--- /dev/null
+++ b/board/Marvell/dns323_b1/Makefile
@@ -0,0 +1,53 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.arib...@free.fr>
+#
+# Based on original Kirkwood support which is
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafu...@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS := dns323_b1.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+clean:
+ rm -f $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/dns323_b1/config.mk
b/board/Marvell/dns323_b1/config.mk
new file mode 100644
index 0000000..3dec1aa
--- /dev/null
+++ b/board/Marvell/dns323_b1/config.mk
@@ -0,0 +1,27 @@
+#
+# Copyright (C) 2010 Albert ARIBAUD <albert.arib...@free.fr>
+#
+# (C) Copyright 2009
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Prafulla Wadaskar <prafu...@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+TEXT_BASE = 0x00100000
diff --git a/board/Marvell/dns323_b1/dns323_b1.c
b/board/Marvell/dns323_b1/dns323_b1.c
new file mode 100644
index 0000000..6cbce9c
--- /dev/null
+++ b/board/Marvell/dns323_b1/dns323_b1.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.arib...@free.fr>
+ *
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafu...@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <miiphy.h>
+#include <asm/arch/orion5x.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The DNS-323 B1 is equipped with a Spansion S29GL064M-90TFI-R4 FLASH
+ * which CFI does not properly detect, hence the LEGACY config.
+ */
+#if defined(CONFIG_FLASH_CFI_LEGACY)
+#include <flash.h>
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ int sectsz[] = CONFIG_SYS_FLASH_SECTSZ;
+ int sect;
+
+ if (base != CONFIG_SYS_FLASH_BASE)
+ return 0;
+
+ info->size = 0;
+ info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+ /* set each sector's start address and size based */
+ for (sect = 0; sect < CONFIG_SYS_MAX_FLASH_SECT; sect++) {
+ info->start[sect] = base+info->size;
+ info->size += sectsz[sect];
+ }
+ /* This flash must be accessed in 8-bits mode, no buffer. */
+ info->flash_id = 0x01000000;
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->buffer_size = 0;
+ /* timings are derived from the Macronix datasheet. */
+ info->erase_blk_tout = 1000;
+ info->write_tout = 10;
+ info->buffer_write_tout = 300;
+ /* Commands and addresses are for AMD mode 8-bit access. */
+ info->vendor = CFI_CMDSET_AMD_LEGACY;
+ info->cmd_reset = 0xF0;
+ info->interface = FLASH_CFI_X8;
+ info->legacy_unlock = 0;
+ info->ext_addr = 0;
+ info->addr_unlock1 = 0x00000aaa;
+ info->addr_unlock2 = 0x00000555;
+ /* Manufacturer Macronix, device MX29LV400CB, CFI 1.3. */
+ info->manufacturer_id = 0x22;
+ info->device_id = 0xBA;
+ info->device_id2 = 0;
+ info->cfi_version = 0x3133;
+ info->cfi_offset = 0x0000;
+ info->name = "MX29LV400CB";
+
+ return 1;
+}
+#endif /* CONFIG_SYS_FLASH_CFI_LEGACY */
+
+int board_init(void)
+{
+ /* arch number of board */
+ gd->bd->bi_arch_number = MACH_TYPE_DNS323;
+
+ /* boot parameter start at 256th byte of RAM base */
+ gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
+
+ return 0;
+}
diff --git a/boards.cfg b/boards.cfg
index da31c36..f04a563 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -254,6 +254,7 @@ sheevaplug arm arm926ejs - Marvell
kirkwood
imx27lite arm arm926ejs imx27lite logicpd mx27
magnesium arm arm926ejs imx27lite logicpd mx27
omap5912osk arm arm926ejs - ti omap
+dns323_b1 arm arm926ejs - Marvell orion5x
edminiv2 arm arm926ejs - LaCie orion5x
omap3_overo arm arm_cortexa8 overo - omap3
omap3_pandora arm arm_cortexa8 pandora - omap3
diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c
index 3267c5d..26011f3 100644
--- a/drivers/mtd/cfi_flash.c
+++ b/drivers/mtd/cfi_flash.c
@@ -32,7 +32,7 @@
*/
/* The DEBUG define must be before common to enable debugging */
-/* #define DEBUG */
+#define DEBUG
#include <common.h>
#include <asm/processor.h>
@@ -2007,9 +2007,9 @@ unsigned long flash_init (void)
size += flash_info[i].size;
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
#ifndef CONFIG_SYS_FLASH_QUIET_TEST
- printf ("## Unknown FLASH on Bank %d "
+ printf ("## Unknown FLASH on Bank %d (%lx) "
"- Size = 0x%08lx = %ld MB\n",
- i+1, flash_info[i].size,
+ i+1, BANK_BASE(i), flash_info[i].size,
flash_info[i].size << 20);
#endif /* CONFIG_SYS_FLASH_QUIET_TEST */
}
diff --git a/include/configs/dns323_b1.h b/include/configs/dns323_b1.h
new file mode 100644
index 0000000..a0467a9
--- /dev/null
+++ b/include/configs/dns323_b1.h
@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2010 Albert ARIBAUD <albert.arib...@free.fr>
+ *
+ * Based on original Kirkwood support which is
+ * (C) Copyright 2009
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Prafulla Wadaskar <prafu...@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CONFIG_DNS323_B1_H
+#define _CONFIG_DNS323_B1_H
+
+/*
+ * Version number information
+ */
+
+#define CONFIG_IDENT_STRING "DNS323_B1"
+
+/*
+ * High Level Configuration Options (easy to change)
+ */
+
+#define CONFIG_MARVELL 1
+#define CONFIG_ARM926EJS 1 /* Basic Architecture */
+#define CONFIG_FEROCEON 1 /* CPU Core subversion */
+#define CONFIG_ORION5X 1 /* SOC Family Name */
+#define CONFIG_88F5182 1 /* SOC Name */
+#define CONFIG_MACH_DNS323 1 /* Machine type */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT 1 /* Skip lowlevel init - makes an
image suitable for chaining from another u-boot loader*/
+
+/*
+ * CLKs configurations
+ */
+
+#define CONFIG_SYS_HZ 1000
+
+/*
+ * Board-specific values for Orion5x MPP low level init:
+ * - MPPs 12 to 15 are SATA LEDs (mode 5)
+ * - Others are GPIO/unused (mode 3 for MPP0, mode 5 for
+ * MPP16 to MPP19, mode 0 for others
+ */
+
+#define ORION5X_MPP0_7 0x00000003
+#define ORION5X_MPP8_15 0x55550000
+#define ORION5X_MPP16_23 0x00000000
+
+/*
+ * Board-specific values for Orion5x GPIO low level init:
+ * - GPIO3 is input (RTC interrupt)
+ * - GPIO16 is Power LED control (0 = on, 1 = off)
+ * - GPIO17 is Power LED source select (0 = CPLD, 1 = GPIO16)
+ * - GPIO18 is Power Button status (0 = Released, 1 = Pressed)
+ * - Last GPIO is 26, further bits are supposed to be 0.
+ * Enable mask has ones for INPUT, 0 for OUTPUT.
+ * Default is LED ON.
+ */
+
+#define ORION5X_GPIO_OUT_ENABLE 0x03fcffff
+#define ORION5X_GPIO_OUT_VALUE 0x03fcffff
+
+/*
+ * NS16550 Configuration
+ */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
+#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
+#define CONFIG_SYS_NS16550_COM1 ORION5X_UART0_BASE
+
+/*
+ * Serial Port configuration
+ * The following definitions let you select what serial you want to use
+ * for your console driver.
+ */
+
+#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600 }
+
+/*
+ * FLASH configuration
+ */
+/* FLASH organization */
+#define ORION5X_DEFADR_BOOTROM 0xff800000
+#define ORION5X_DEFSZ_BOOTROM (8*1024*1024)
+
+#define CONFIG_SYS_FLASH_CFI
+#ifdef CONFIG_SYS_FLASH_CFI
+# define CONFIG_FLASH_CFI_DRIVER 1
+# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
+# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of
memory banks */
+# define CONFIG_SYS_MAX_FLASH_SECT 254 /* max number of
sectors on one chip */
+# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors
protection */
+#endif
+
+#define CONFIG_SYS_FLASH_BASE 0xff800000
+
+/* auto boot */
+#define CONFIG_BOOTDELAY -1 /* default disable autoboot */
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
+#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
+#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
+
+#define CONFIG_SYS_PROMPT "DNS323B1> " /* Command Prompt */
+#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+ +sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
+/*
+ * Commands configuration - using default command set for now
+ */
+#include <config_cmd_default.h>
+/*
+ * Disabling some default commands for staggered bring-up
+ */
+#undef CONFIG_CMD_BOOTD /* no bootd since no net */
+#undef CONFIG_CMD_NET /* no net since no eth */
+#undef CONFIG_CMD_NFS /* no NFS since no net */
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_SECT_SIZE 0x2000 /* 16K */
+#define CONFIG_ENV_SIZE 0x2000
+#define CONFIG_ENV_OFFSET 0x4000 /* env starts here */
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN (1024 * 128) /* 128kB for malloc() */
+/* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+
+/*
+ * Other required minimal configurations
+ */
+#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
+#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
+#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
+#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_STACKSIZE 0x00100000
+#define CONFIG_SYS_LOAD_ADDR 0x00800000
+#define CONFIG_SYS_MEMTEST_START 0x00400000
+#define CONFIG_SYS_MEMTEST_END 0x007fffff
+#define CONFIG_SYS_RESET_ADDRESS 0xffff0000
+#define CONFIG_SYS_MAXARGS 16
+
+#endif /* _CONFIG_DNS323_B1_H */
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