Hi Priyanka, Please see my reply inline.
> -----Original Message----- > From: Priyanka Jain > Sent: 2019年9月25日 13:05 > To: Andy Tang <andy.t...@nxp.com>; Priyanka Jain <priyanka.j...@nxp.com> > Cc: Andy Tang <andy.t...@nxp.com>; u-boot@lists.denx.de > Subject: RE: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities > support > > > > >-----Original Message----- > >From: U-Boot <u-boot-boun...@lists.denx.de> On Behalf Of Yuantian Tang > >Sent: Wednesday, September 18, 2019 2:21 PM > >To: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com> > >Cc: Andy Tang <andy.t...@nxp.com>; u-boot@lists.denx.de > >Subject: [U-Boot] [PATCH v2] armv8: ls1028a: add more personalities > >support > > > Please update subject to be more specific about Soc personalities. > Something like > armv8: ls1028a: add LS1027A, LS1018A, LS1017A support you can skip this > line in description Any reason it must be put in patch subject? BR, Andy > > --priyankajain > >Add LS1027A, LS1018A and LS1017A personalities support to LS1028A > >processor soc family. > > > >LS1028A processor is the prime personality of LS1028A soc family. > >LS1027A processor is a lower funtionality version of QorIQ LS1028A > >which does not support the multimedia subsystems, such as LCD > >controller, GPU, and eDP PHY. > >The QorIQ LS1018A and LS1017A are low power versions of the QorIQ > >LS1028A and LS1027A processors, respectively which integrate single > >64-bit Arm A72 core. > > > >Signed-off-by: Tang Yuantian <andy.t...@nxp.com> > >--- > >v2: > > - refine description > > arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 3 +++ > > arch/arm/include/asm/arch-fsl-layerscape/soc.h | 3 +++ > > 2 files changed, 6 insertions(+) > > > >diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > >b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > >index 3e2a24fe80..dee96afe2d 100644 > >--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > >+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c > >@@ -58,6 +58,9 @@ static struct cpu_type cpu_type_list[] = { > > CPU_TYPE_ENTRY(LS1026A, LS1026A, 2), > > CPU_TYPE_ENTRY(LS2040A, LS2040A, 4), > > CPU_TYPE_ENTRY(LS1012A, LS1012A, 1), > >+ CPU_TYPE_ENTRY(LS1017A, LS1017A, 1), > >+ CPU_TYPE_ENTRY(LS1018A, LS1018A, 1), > >+ CPU_TYPE_ENTRY(LS1027A, LS1027A, 2), > > CPU_TYPE_ENTRY(LS1028A, LS1028A, 2), > > CPU_TYPE_ENTRY(LS1088A, LS1088A, 8), > > CPU_TYPE_ENTRY(LS1084A, LS1084A, 8), > >diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > >b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > > > >--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h > >+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h > >@@ -83,6 +83,9 @@ enum boot_src get_boot_src(void); > > /* LS1043A/LS1023A 23x23 package silicon has different value of VAR_PER > */ > > #define SVR_LS1043A_P23 0x879202 > > #define SVR_LS1023A_P23 0x87920A > >+#define SVR_LS1017A 0x870B24 > >+#define SVR_LS1018A 0x870B20 > >+#define SVR_LS1027A 0x870B04 > > #define SVR_LS1028A 0x870B00 > > #define SVR_LS1046A 0x870700 > > #define SVR_LS1026A 0x870708 > >-- > >2.17.1 > > > >_______________________________________________ > >U-Boot mailing list > >U-Boot@lists.denx.de > >https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists > >.de > >nx.de%2Flistinfo%2Fu- > >boot&data=02%7C01%7Cpriyanka.jain%40nxp.com%7Cad5af7711fa64 > 03 > >9450208d73c16cc16%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0% > 7C > >637043940922465590&sdata=dtSR0EQhGhJYBzhKAOWWGCMRbxYax > %2F > >uuJmKY%2FKAhQBY%3D&reserved=0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot