From: Hou Zhiqiang <zhiqiang....@nxp.com>
P2020 integrated 3 PCIe controllers, which is compatible with
the PCI Express™ Base Specification, Revision 1.0a, and this
patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
Reviewed-by: Bin Meng <bmeng...@gmail.com>
---
V2:
- Rebased the patch.
arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++++++++++++++++++++++
arch/powerpc/dts/p2020rdb-pc.dts | 17 ++++++++++++++++
arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 ++++++++++++++++
3 files changed, 64 insertions(+)
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi
index f20d1fa20d..f696f35960 100644
--- a/arch/powerpc/dts/p2020-post.dtsi
+++ b/arch/powerpc/dts/p2020-post.dtsi
@@ -25,3 +25,33 @@
last-interrupt-source = <255>;
};
};
+
+/* PCIe controller base address 0x8000 */
+&pci2 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0x9000 */
+&pci1 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
+
+/* PCIe controller base address 0xa000 */
+&pci0 {
+ compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
+ law_trgt_if = <2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x0 0xff>;
+};
diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts
index 4800b76c1c..08befd4c59 100644
--- a/arch/powerpc/dts/p2020rdb-pc.dts
+++ b/arch/powerpc/dts/p2020rdb-pc.dts
@@ -18,6 +18,23 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
+
+ pci2: pcie@ffe08000 {
+ reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@ffe09000 {
+ reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0
0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0
0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@ffe0a000 {
+ reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0
0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0
0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p2020-post.dtsi"
diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts
b/arch/powerpc/dts/p2020rdb-pc_36b.dts
index 8323b90e6d..04b2519e1a 100644
--- a/arch/powerpc/dts/p2020rdb-pc_36b.dts
+++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts
@@ -18,6 +18,23 @@
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
+
+ pci2: pcie@fffe08000 {
+ reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
+ status = "disabled";
+ };
+
+ pci1: pcie@fffe09000 {
+ reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0
0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0
0x20000000>; /* non-prefetchable memory */
+ };
+
+ pci0: pcie@fffe0a000 {
+ reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
+ ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0
0x00010000 /* downstream I/O */
+ 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0
0x20000000>; /* non-prefetchable memory */
+ };
};
/include/ "p2020-post.dtsi"
--
2.17.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
