From: Bai Ping <ping....@nxp.com>
On i.MX7ULP, value zero is reserved in SCG1 RCCR register,
so the val should be decreased by 1 to get the correct clock
source index.
Signed-off-by: Bai Ping <ping....@nxp.com>
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/mach-imx/mx7ulp/scg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/mx7ulp/scg.c b/arch/arm/mach-imx/mx7ulp/scg.c
index b4f2ea875a..85d726fe30 100644
--- a/arch/arm/mach-imx/mx7ulp/scg.c
+++ b/arch/arm/mach-imx/mx7ulp/scg.c
@@ -440,7 +440,7 @@ static u32 scg_sys_get_rate(enum scg_clk clk)
case SCG_SCS_SLOW_IRC:
case SCG_SCS_FAST_IRC:
case SCG_SCS_RTC_OSC:
- rate = scg_src_get_rate(scg_scs_array[val]);
+ rate = scg_src_get_rate(scg_scs_array[val - 1]);
break;
case 5:
rate = scg_apll_get_rate();
--
2.16.4
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