Add dram config macro for handling cs1 column.

Signed-off-by: Jagan Teki <[email protected]>
Signed-off-by: YouMin Chen <[email protected]>
---
 arch/arm/include/asm/arch-rockchip/sdram_common.h | 3 +++
 drivers/ram/rockchip/sdram_rk3399.c               | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-rockchip/sdram_common.h 
b/arch/arm/include/asm/arch-rockchip/sdram_common.h
index 9cd9f3b969..f5c99fea8b 100644
--- a/arch/arm/include/asm/arch-rockchip/sdram_common.h
+++ b/arch/arm/include/asm/arch-rockchip/sdram_common.h
@@ -113,6 +113,9 @@ struct sdram_base_params {
                                     (4 + 2 * (ch)); \
                } while (0)
 
+#define SYS_REG_CS1_COL_SHIFT(ch)      (0 + 2 * (ch))
+#define SYS_REG_ENC_CS1_COL(n, ch)      (((n) - 9) << 
SYS_REG_CS1_COL_SHIFT(ch))
+
 /* Get sdram size decode from reg */
 size_t rockchip_sdram_size(phys_addr_t reg);
 
diff --git a/drivers/ram/rockchip/sdram_rk3399.c 
b/drivers/ram/rockchip/sdram_rk3399.c
index 1222da39c2..0f28163d6e 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1101,6 +1101,7 @@ static void dram_all_config(struct dram_info *dram,
                if (info->cap_info.cs1_row)
                        SYS_REG_ENC_CS1_ROW(info->cap_info.cs1_row, sys_reg2,
                                            sys_reg3, channel);
+               sys_reg3 |= SYS_REG_ENC_CS1_COL(info->cap_info.col, channel);
 
                ddr_msch_regs = dram->chan[channel].msch;
                noc_timing = &params->ch[channel].noc_timings;
-- 
2.18.0.321.gffc6fa0e3

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