set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan <peng....@nxp.com> --- arch/arm/mach-imx/imx8m/soc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 5bbc3f4f1d..9a90383f51 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -59,6 +59,8 @@ void enable_tzc380(void) /* Enable TZASC and lock setting */ setbits_le32(&gpr->gpr[10], GPR_TZASC_EN); setbits_le32(&gpr->gpr[10], GPR_TZASC_EN_LOCK); + if (IS_ENABLED(CONFIG_IMX8MM)) + setbits_le32(&gpr->gpr[10], BIT(1)); } void set_wdog_reset(struct wdog_regs *wdog) -- 2.16.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot