Move all the tag "u-boot,dm-pre-reloc" from rk3288.dtsi
into rk3288-u-boot.dtsi.
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
---
Changes in v3:
- include "rk3288-u-boot.dtsi" for board already have board
level -u-boot.dtsi
Changes in v2: None
arch/arm/dts/rk3288-u-boot.dtsi | 36 +++++++++++++++++++++++++++
arch/arm/dts/rk3288-veyron-speedy.dts | 1 +
arch/arm/dts/rk3288-vyasa.dts | 1 +
arch/arm/dts/rk3288.dtsi | 8 ------
4 files changed, 38 insertions(+), 8 deletions(-)
create mode 100644 arch/arm/dts/rk3288-u-boot.dtsi
diff --git a/arch/arm/dts/rk3288-u-boot.dtsi b/arch/arm/dts/rk3288-u-boot.dtsi
new file mode 100644
index 0000000000..4cf75c7504
--- /dev/null
+++ b/arch/arm/dts/rk3288-u-boot.dtsi
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Rockchip Electronics Co., Ltd
+ */
+
+&dmc {
+ u-boot,dm-pre-reloc;
+};
+
+&pmu {
+ u-boot,dm-pre-reloc;
+};
+
+&sgrf {
+ u-boot,dm-pre-reloc;
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&vopb {
+ u-boot,dm-pre-reloc;
+};
+
+&vopl {
+ u-boot,dm-pre-reloc;
+};
+
+&noc {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/rk3288-veyron-speedy.dts
b/arch/arm/dts/rk3288-veyron-speedy.dts
index 58c1fe96ee..b2c91b3fe5 100644
--- a/arch/arm/dts/rk3288-veyron-speedy.dts
+++ b/arch/arm/dts/rk3288-veyron-speedy.dts
@@ -8,6 +8,7 @@
/dts-v1/;
#include "rk3288-veyron-chromebook.dtsi"
#include "cros-ec-sbs.dtsi"
+#include "rk3288-u-boot.dtsi"
#include "rk3288-veyron-speedy-u-boot.dtsi"
/ {
diff --git a/arch/arm/dts/rk3288-vyasa.dts b/arch/arm/dts/rk3288-vyasa.dts
index 850aa25818..12aabf3203 100644
--- a/arch/arm/dts/rk3288-vyasa.dts
+++ b/arch/arm/dts/rk3288-vyasa.dts
@@ -42,6 +42,7 @@
/dts-v1/;
#include "rk3288.dtsi"
+#include "rk3288-u-boot.dtsi"
/ {
model = "Amarula Vyasa-RK3288";
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi
index 487d22c9b0..866fc08215 100644
--- a/arch/arm/dts/rk3288.dtsi
+++ b/arch/arm/dts/rk3288.dtsi
@@ -468,7 +468,6 @@
};
dmc: dmc@ff610000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-dmc", "syscon";
rockchip,cru = <&cru>;
rockchip,grf = <&grf>;
@@ -584,13 +583,11 @@
};
pmu: power-management@ff730000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-pmu", "syscon";
reg = <0xff730000 0x100>;
};
sgrf: syscon@ff740000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-sgrf", "syscon";
reg = <0xff740000 0x1000>;
};
@@ -599,7 +596,6 @@
compatible = "rockchip,rk3288-cru";
reg = <0xff760000 0x1000>;
rockchip,grf = <&grf>;
- u-boot,dm-pre-reloc;
#clock-cells = <1>;
#reset-cells = <1>;
assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
@@ -615,7 +611,6 @@
};
grf: syscon@ff770000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-grf", "syscon";
reg = <0xff770000 0x1000>;
};
@@ -660,7 +655,6 @@
};
vopb: vop@ff930000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-vop";
reg = <0xff930000 0x19c>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
@@ -715,7 +709,6 @@
iommus = <&vopl_mmu>;
power-domains = <&power RK3288_PD_VIO>;
status = "disabled";
- u-boot,dm-pre-reloc;
vopl_out: port {
#address-cells = <1>;
#size-cells = <0>;
@@ -911,7 +904,6 @@
};
noc: syscon@ffac0000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3288-noc", "syscon";
reg = <0xffac0000 0x2000>;
};
--
2.20.1
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