> -----Original Message----- > From: Yinbo Zhu <yinbo....@nxp.com> > Sent: Monday, June 3, 2019 4:54 PM > To: York Sun <york....@nxp.com>; u-boot@lists.denx.de; Prabhakar Kushwaha > <prabhakar.kushw...@nxp.com>; Vabhav Sharma <vabhav.sha...@nxp.com>; > Ashish Kumar <ashish.ku...@nxp.com> > Cc: Yinbo Zhu <yinbo....@nxp.com>; Xiaobo Xie <xiaobo....@nxp.com>; Jiafei > Pan <jiafei....@nxp.com>; Y.b. Lu <yangbo...@nxp.com>; Jagdish Gediya > <jagdish.ged...@nxp.com> > Subject: [PATCH v3] armv8: fsl-lsch2: add clock support for the second eSDHC > > Layerscape began to use two eSDHC controllers, for example, LS1012A. They > are same IP block with same reference clock. > This patch is to add clock support for the second eSDHC. > > Signed-off-by: Yinbo Zhu <yinbo....@nxp.com> > --- > Change in v2: > Update the Copyright information > > Change in v3: > Add "* Copyright 2019 NXP." > > arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c | 2 ++ > 1 file changed, 2 insertions(+) >
This patch has been applied to fsl-qoriq master, awaiting upstream. --pk _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
