The DRAM controller manual suggests to first program the PHY
initialisation parameters to the PHY_PIR register, and then set bit 0 to
trigger the initialisation. This is also used in boot0.
Follow this recommendation by setting bit 0 in a separate step.
Signed-off-by: Andre Przywara <andre.przyw...@arm.com>
---
arch/arm/mach-sunxi/dram_sun50i_h6.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c
b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index e2f141eb9b..7a8b724f08 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -75,12 +75,14 @@ static void mctl_core_init(struct dram_para *para)
mctl_channel_init(para);
}
+/* PHY initialisation */
static void mctl_phy_pir_init(u32 val)
{
struct sunxi_mctl_phy_reg * const mctl_phy =
(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
- writel(val | BIT(0), &mctl_phy->pir);
+ writel(val, &mctl_phy->pir);
+ writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
}
--
2.14.5
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