Add support for setting 50MHz ddr clock.

Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Signed-off-by: YouMin Chen <c...@rock-chips.com>
---
 drivers/clk/rockchip/clk_rk3399.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
b/drivers/clk/rockchip/clk_rk3399.c
index 5d1ad94e85..1de21c9f3e 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -827,6 +827,10 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru,
 
        /*  clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
        switch (set_rate) {
+       case 50 * MHz:
+               dpll_cfg = (struct pll_div)
+               {.refdiv = 1, .fbdiv = 12, .postdiv1 = 3, .postdiv2 = 2};
+               break;
        case 200 * MHz:
                dpll_cfg = (struct pll_div)
                {.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
-- 
2.18.0.321.gffc6fa0e3

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