The hardware for LPDDR4 with
- CLK0P/N connect to lower 16-bits
- CLK1P/N connect to higher 16-bits
and usually dfi dram clk is configured via CLK1P/N, so
disabling dfi dram clk will disable the CLK1P/N as well.
So, add patch to not to disable dfi dram clk for lpddr4,
with rank 1.
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
Signed-off-by: YouMin Chen <c...@rock-chips.com>
---
drivers/ram/rockchip/sdram_rk3399.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/ram/rockchip/sdram_rk3399.c
b/drivers/ram/rockchip/sdram_rk3399.c
index 41dd19a9e6..d1b3aeef47 100644
--- a/drivers/ram/rockchip/sdram_rk3399.c
+++ b/drivers/ram/rockchip/sdram_rk3399.c
@@ -1226,8 +1226,18 @@ static void dram_all_config(struct dram_info *dram,
writel(noc_timing->ddrmode.d32,
&ddr_msch_regs->ddrmode);
- /* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
- if (params->ch[channel].cap_info.rank == 1)
+ /**
+ * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
+ *
+ * The hardware for LPDDR4 with
+ * - CLK0P/N connect to lower 16-bits
+ * - CLK1P/N connect to higher 16-bits
+ *
+ * dfi dram clk is configured via CLK1P/N, so disabling
+ * dfi dram clk will disable the CLK1P/N as well for lpddr4.
+ */
+ if (params->ch[channel].cap_info.rank == 1 &&
+ params->base.dramtype != LPDDR4)
setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1 << 17);
}
--
2.18.0.321.gffc6fa0e3
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