Move Stratix10 and Agilex system manager common code new header file.
Signed-off-by: Ley Foon Tan <ley.foon....@intel.com>
---
.../include/mach/system_manager_s10.h | 46 +--------------
.../mach/system_manager_s10_agilex_common.h | 59 +++++++++++++++++++
2 files changed, 60 insertions(+), 45 deletions(-)
create mode 100644
arch/arm/mach-socfpga/include/mach/system_manager_s10_agilex_common.h
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
index 297f9e1999..af8cfc9f05 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h
@@ -7,14 +7,6 @@
#ifndef _SYSTEM_MANAGER_S10_
#define _SYSTEM_MANAGER_S10_
-void sysmgr_pinmux_init(void);
-void populate_sysmgr_fpgaintf_module(void);
-void populate_sysmgr_pinmux(void);
-void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
-void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
-
struct socfpga_system_manager {
/* System Manager Module */
u32 siliconid1; /* 0x00 */
@@ -135,42 +127,6 @@ struct socfpga_system_manager {
};
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
-#define SYSMGR_ECC_OCRAM_EN BIT(0)
-#define SYSMGR_ECC_OCRAM_SERR BIT(3)
-#define SYSMGR_ECC_OCRAM_DERR BIT(4)
-#define SYSMGR_FPGAINTF_USEFPGA 0x1
-
-#define SYSMGR_FPGAINTF_NAND BIT(4)
-#define SYSMGR_FPGAINTF_SDMMC BIT(8)
-#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
-#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
-#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
-#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
-#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
-
-#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
-#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
-
-/* EMAC Group Bit definitions */
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
-
-#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
-#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
-
-#define SYSMGR_NOC_H2F_MSK 0x00000001
-#define SYSMGR_NOC_LWH2F_MSK 0x00000010
-#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
-
-#define SYSMGR_DMA_IRQ_NS 0xFF000000
-#define SYSMGR_DMA_MGR_NS 0x00010000
-
-#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
-
-#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#include <asm/arch/system_manager_s10_agilex_common.h>
#endif /* _SYSTEM_MANAGER_S10_ */
diff --git
a/arch/arm/mach-socfpga/include/mach/system_manager_s10_agilex_common.h
b/arch/arm/mach-socfpga/include/mach/system_manager_s10_agilex_common.h
new file mode 100644
index 0000000000..fe8ddce548
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10_agilex_common.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _SYSTEM_MANAGER_S10_AGILEX_COMMON_H_
+#define _SYSTEM_MANAGER_S10_AGILEX_COMMON_H_
+
+#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+
+void sysmgr_pinmux_init(void);
+void populate_sysmgr_fpgaintf_module(void);
+void populate_sysmgr_pinmux(void);
+void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len);
+void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0)
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1)
+#define SYSMGR_ECC_OCRAM_EN BIT(0)
+#define SYSMGR_ECC_OCRAM_SERR BIT(3)
+#define SYSMGR_ECC_OCRAM_DERR BIT(4)
+#define SYSMGR_FPGAINTF_USEFPGA 0x1
+
+#define SYSMGR_FPGAINTF_NAND BIT(4)
+#define SYSMGR_FPGAINTF_SDMMC BIT(8)
+#define SYSMGR_FPGAINTF_SPIM0 BIT(16)
+#define SYSMGR_FPGAINTF_SPIM1 BIT(24)
+#define SYSMGR_FPGAINTF_EMAC0 BIT(0)
+#define SYSMGR_FPGAINTF_EMAC1 BIT(8)
+#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
+
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4
+#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
+
+/* EMAC Group Bit definitions */
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0
+#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+
+#define SYSMGR_NOC_H2F_MSK 0x00000001
+#define SYSMGR_NOC_LWH2F_MSK 0x00000010
+#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
+
+#define SYSMGR_DMA_IRQ_NS 0xFF000000
+#define SYSMGR_DMA_MGR_NS 0x00010000
+
+#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
+
+#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+
+#endif
+
+#endif /* _SYSTEM_MANAGER_S10_AGILEX_COMMON_H_ */
--
2.19.0
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