On 05/07/2019 04:58 PM, Christoph Muellner wrote: > This patch adds the rate for UART1 and UART3 the same way > as already implemented for UART0 and UART2. > > This is required for boards, which have their console output > on these UARTs. > > Signed-off-by: Christoph Muellner <christoph.muell...@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.y...@rock-chips.com> Thanks, - Kever > --- > > drivers/clk/rockchip/clk_rk3399.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/clk/rockchip/clk_rk3399.c > b/drivers/clk/rockchip/clk_rk3399.c > index 93a652e5ff..aa6a8ad1c9 100644 > --- a/drivers/clk/rockchip/clk_rk3399.c > +++ b/drivers/clk/rockchip/clk_rk3399.c > @@ -912,7 +912,9 @@ static ulong rk3399_clk_get_rate(struct clk *clk) > rate = rk3399_spi_get_clk(priv->cru, clk->id); > break; > case SCLK_UART0: > + case SCLK_UART1: > case SCLK_UART2: > + case SCLK_UART3: > return 24000000; > break; > case PCLK_HDMI_CTRL: _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
