Few platforms need longer timeout to flush l3 cache. This patch increase the timeout value for proper l3 cache flush operation.
Signed-off-by: Udit Kumar <udit.ku...@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggar...@nxp.com> --- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 6721a57..10aebbc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -362,7 +362,7 @@ hnf_pstate_poll: mov x1, x0 mov x7, #0 /* flag for timeout */ mrs x3, cntpct_el0 /* read timer */ - add x3, x3, #1200 /* timeout after 100 microseconds */ + add x3, x3, #4000 /* timeout after 333 microseconds */ mov x0, #0x18 movk x0, #0x420, lsl #16 /* HNF0_PSTATE_STATUS */ mov w6, #8 /* HN-F node count */ -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot