Since there is no register for CPU revision, we use ROM version to
check the A0 or B0 chip.
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/mach-imx/mx7ulp/soc.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index 7119ee4a07..6c53aa106e 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -18,10 +18,13 @@ struct imx_sec_config_fuse_t const imx_sec_config_fuse = {
};
#endif
+#define ROM_VERSION_ADDR 0x80
u32 get_cpu_rev(void)
{
- /* Temporally hard code the CPU rev to 0x73, rev 1.0. Fix it later */
- return (MXC_CPU_MX7ULP << 12) | (1 << 4);
+ /* Check the ROM version for cpu revision */
+ u32 rom_version = readl((void __iomem *)ROM_VERSION_ADDR);
+
+ return (MXC_CPU_MX7ULP << 12) | (rom_version & 0xFF);
}
#ifdef CONFIG_REVISION_TAG
--
2.16.4
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