The ULP watchdog is not used in mainline U-Boot at all. This patch
removes the driver and its references (CONFIG_ULP_WATCHDOG) completely.
Signed-off-by: Stefan Roese <s...@denx.de>
Cc: Peng Fan <peng....@nxp.com>
Cc: Ye Li <ye...@nxp.com>
Cc: Stefano Babic <sba...@denx.de>
---
arch/arm/mach-imx/mx7ulp/soc.c | 2 -
drivers/watchdog/Kconfig | 5 --
drivers/watchdog/Makefile | 1 -
drivers/watchdog/ulp_wdog.c | 95 ----------------------------------
4 files changed, 103 deletions(-)
delete mode 100644 drivers/watchdog/ulp_wdog.c
diff --git a/arch/arm/mach-imx/mx7ulp/soc.c b/arch/arm/mach-imx/mx7ulp/soc.c
index c72f0ed3fc..cd7b96b5d8 100644
--- a/arch/arm/mach-imx/mx7ulp/soc.c
+++ b/arch/arm/mach-imx/mx7ulp/soc.c
@@ -108,14 +108,12 @@ void s_init(void)
return;
}
-#ifndef CONFIG_ULP_WATCHDOG
void reset_cpu(ulong addr)
{
setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
while (1)
;
}
-#endif
#if defined(CONFIG_DISPLAY_CPUINFO)
const char *get_imx_type(u32 imxtype)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index f909d40f45..e2a6a27b2a 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -43,11 +43,6 @@ config TANGIER_WATCHDOG
Intel Tangier SoC. If you're using a board with Intel Tangier
SoC, say Y here.
-config ULP_WATCHDOG
- bool "i.MX7ULP watchdog"
- help
- Say Y here to enable i.MX7ULP watchdog driver.
-
config WDT
bool "Enable driver model for watchdog timer drivers"
depends on DM
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 40b2f4bc66..3e3b60b00d 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,7 +15,6 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
obj-$(CONFIG_TANGIER_WATCHDOG) += tangier_wdt.o
-obj-$(CONFIG_ULP_WATCHDOG) += ulp_wdog.o
obj-$(CONFIG_WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
diff --git a/drivers/watchdog/ulp_wdog.c b/drivers/watchdog/ulp_wdog.c
deleted file mode 100644
index 313019f152..0000000000
--- a/drivers/watchdog/ulp_wdog.c
+++ /dev/null
@@ -1,95 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2016 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/imx-regs.h>
-
-/*
- * MX7ULP WDOG Register Map
- */
-struct wdog_regs {
- u8 cs1;
- u8 cs2;
- u16 reserve0;
- u32 cnt;
- u32 toval;
- u32 win;
-};
-
-#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
-#define CONFIG_WATCHDOG_TIMEOUT_MSECS 0x1500
-#endif
-
-#define REFRESH_WORD0 0xA602 /* 1st refresh word */
-#define REFRESH_WORD1 0xB480 /* 2nd refresh word */
-
-#define UNLOCK_WORD0 0xC520 /* 1st unlock word */
-#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
-
-#define WDGCS1_WDGE (1<<7)
-#define WDGCS1_WDGUPDATE (1<<5)
-
-#define WDGCS2_FLG (1<<6)
-
-#define WDG_BUS_CLK (0x0)
-#define WDG_LPO_CLK (0x1)
-#define WDG_32KHZ_CLK (0x2)
-#define WDG_EXT_CLK (0x3)
-
-void hw_watchdog_set_timeout(u16 val)
-{
- /* setting timeout value */
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
- writel(val, &wdog->toval);
-}
-
-void hw_watchdog_reset(void)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
- writel(REFRESH_WORD0, &wdog->cnt);
- writel(REFRESH_WORD1, &wdog->cnt);
-}
-
-void hw_watchdog_init(void)
-{
- u8 val;
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
- writel(UNLOCK_WORD0, &wdog->cnt);
- writel(UNLOCK_WORD1, &wdog->cnt);
-
- val = readb(&wdog->cs2);
- val |= WDGCS2_FLG;
- writeb(val, &wdog->cs2);
-
- hw_watchdog_set_timeout(CONFIG_WATCHDOG_TIMEOUT_MSECS);
- writel(0, &wdog->win);
-
- writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
- writeb((WDGCS1_WDGE | WDGCS1_WDGUPDATE), &wdog->cs1);/* enable counter
running */
-
- hw_watchdog_reset();
-}
-
-void reset_cpu(ulong addr)
-{
- struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
-
- writel(UNLOCK_WORD0, &wdog->cnt);
- writel(UNLOCK_WORD1, &wdog->cnt);
-
- hw_watchdog_set_timeout(5); /* 5ms timeout */
- writel(0, &wdog->win);
-
- writeb(WDG_LPO_CLK, &wdog->cs2);/* setting 1-kHz clock source */
- writeb(WDGCS1_WDGE, &wdog->cs1);/* enable counter running */
-
- hw_watchdog_reset();
-
- while (1);
-}
--
2.21.0
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