Add OSTM timer driver for RZ/A1 SoC. The IP is very different
from the R-Car Gen2/Gen3 one already present in the tree, hence
a custom driver.
Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Chris Brandt <chris.bra...@renesas.com>
Cc: Nobuhiro Iwamatsu <iwama...@nigauri.org>
---
drivers/timer/Kconfig | 7 +++
drivers/timer/Makefile | 1 +
drivers/timer/ostm_timer.c | 92 ++++++++++++++++++++++++++++++++++++++
3 files changed, 100 insertions(+)
create mode 100644 drivers/timer/ostm_timer.c
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index df37a798bd..5f4bc6edb6 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -110,6 +110,13 @@ config MPC83XX_TIMER
Select this to enable support for the timer found on
devices based on the MPC83xx family of SoCs.
+config RENESAS_OSTM_TIMER
+ bool "Renesas RZ/A1 R7S72100 OSTM Timer"
+ depends on TIMER
+ help
+ Enables support for the Renesas OSTM Timer driver.
+ This timer is present on Renesas RZ/A1 R7S72100 SoCs.
+
config X86_TSC_TIMER_EARLY_FREQ
int "x86 TSC timer frequency in MHz when used as the early timer"
depends on X86_TSC_TIMER
diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile
index d0bf218b11..fa35bea6c5 100644
--- a/drivers/timer/Makefile
+++ b/drivers/timer/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_CADENCE_TTC_TIMER) += cadence-ttc.o
obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
obj-$(CONFIG_MPC83XX_TIMER) += mpc83xx_timer.o
obj-$(CONFIG_OMAP_TIMER) += omap-timer.o
+obj-$(CONFIG_RENESAS_OSTM_TIMER) += ostm_timer.o
obj-$(CONFIG_RISCV_TIMER) += riscv_timer.o
obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
obj-$(CONFIG_SANDBOX_TIMER) += sandbox_timer.o
diff --git a/drivers/timer/ostm_timer.c b/drivers/timer/ostm_timer.c
new file mode 100644
index 0000000000..f0e25093ca
--- /dev/null
+++ b/drivers/timer/ostm_timer.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Renesas RZ/A1 R7S72100 OSTM Timer driver
+ *
+ * Copyright (C) 2019 Marek Vasut <marek.va...@gmail.com>
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <dm.h>
+#include <clk.h>
+#include <timer.h>
+
+#define OSTM_CMP 0x00
+#define OSTM_CNT 0x04
+#define OSTM_TE 0x10
+#define OSTM_TS 0x14
+#define OSTM_TT 0x18
+#define OSTM_CTL 0x20
+#define OSTM_CTL_D BIT(1)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ostm_priv {
+ fdt_addr_t regs;
+};
+
+static int ostm_get_count(struct udevice *dev, u64 *count)
+{
+ struct ostm_priv *priv = dev_get_priv(dev);
+
+ *count = timer_conv_64(readl(priv->regs + OSTM_CNT));
+
+ return 0;
+}
+
+static int ostm_probe(struct udevice *dev)
+{
+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ struct ostm_priv *priv = dev_get_priv(dev);
+#if CONFIG_IS_ENABLED(CLK)
+ struct clk clk;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret)
+ return ret;
+
+ uc_priv->clock_rate = clk_get_rate(&clk);
+
+ clk_free(&clk);
+#else
+ uc_priv->clock_rate = CONFIG_SYS_CLK_FREQ / 2;
+#endif
+
+ readb(priv->regs + OSTM_CTL);
+ writeb(OSTM_CTL_D, priv->regs + OSTM_CTL);
+
+ setbits_8(priv->regs + OSTM_TT, BIT(0));
+ writel(0xffffffff, priv->regs + OSTM_CMP);
+ setbits_8(priv->regs + OSTM_TS, BIT(0));
+
+ return 0;
+}
+
+static int ostm_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ostm_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr(dev);
+
+ return 0;
+}
+
+static const struct timer_ops ostm_ops = {
+ .get_count = ostm_get_count,
+};
+
+static const struct udevice_id ostm_ids[] = {
+ { .compatible = "renesas,ostm" },
+ {}
+};
+
+U_BOOT_DRIVER(ostm_timer) = {
+ .name = "ostm-timer",
+ .id = UCLASS_TIMER,
+ .ops = &ostm_ops,
+ .probe = ostm_probe,
+ .of_match = ostm_ids,
+ .ofdata_to_platdata = ostm_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct ostm_priv),
+};
--
2.20.1
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