On 4/16/19 10:08 PM, Simon Goldschmidt wrote: > Hi Marek, > > Am 12.04.2019 um 12:31 schrieb Marek Vasut: >> On 4/11/19 10:07 PM, Simon Goldschmidt wrote: >>> >>> >>> Marek Vasut <ma...@denx.de <mailto:ma...@denx.de>> schrieb am Do., 11. >>> Apr. 2019, 21:59: >>> >>> On 4/11/19 9:30 PM, Simon Goldschmidt wrote: >>> > >>> > >>> > On 11.04.19 21:03, Tom Rini wrote: >>> >> On Thu, Apr 11, 2019 at 08:49:38PM +0200, Simon Goldschmidt >>> wrote: >>> >>> >>> >>> >>> >>> On 11.04.19 20:20, Tom Rini wrote: >>> >>>> On Thu, Apr 11, 2019 at 08:19:38PM +0200, Marek Vasut wrote: >>> >>>>> On 4/11/19 8:17 PM, Tom Rini wrote: >>> >>>>>> On Wed, Apr 10, 2019 at 04:46:28PM +0200, Marek Vasut wrote: >>> >>>>>> >>> >>>>>>> The following changes since commit >>> >>>>>>> 3c99166441bf3ea325af2da83cfe65430b49c066: >>> >>>>>>> >>> >>>>>>> Prepare v2019.04 (2019-04-08 21:40:40 -0400) >>> >>>>>>> >>> >>>>>>> are available in the Git repository at: >>> >>>>>>> >>> >>>>>>> git://git.denx.de/u-boot-socfpga.git >>> <http://git.denx.de/u-boot-socfpga.git> master >>> >>>>>>> >>> >>>>>>> for you to fetch changes up to >>> >>>>>>> ef8679b24ec6226b7198e06747ff047a16030ca4: >>> >>>>>>> >>> >>>>>>> arm: dts: Stratix10: Add QSPI node (2019-04-09 13:11:06 >>> +0200) >>> >>>>>>> >>> >>>>>> >>> >>>>>> Arg, sorry I didn't see this sooner: >>> >>>>>> arm: w+ socfpga_arria10 >>> >>>>>> +(socfpga_arria10) >>> >>>>>> +(socfpga_arria10) WARNING: unmet direct dependencies >>> detected for >>> >>>>>> ALTERA_SDRAM >>> >>>>>> +(socfpga_arria10) Depends on [n]: RAM [=n] && >>> >>>>>> (TARGET_SOCFPGA_GEN5 [=n] || TARGET_SOCFPGA_ARRIA10 [=y]) >>> >>>>>> +(socfpga_arria10) Selected by [y]: >>> >>>>>> +(socfpga_arria10) - TARGET_SOCFPGA_ARRIA10 [=y] && ARM >>> [=y] && >>> >>>>>> ARCH_SOCFPGA [=y] >>> >>>>> >>> >>>>> Is this coming from this PR or not ? >>> >>>> >>> >>>> Yes, this PR. Top of tree + this PR only. >>> >>> >>> >>> It's not only top of tree + this PR, it also fails for pure >>> >>> u-boot-socfpga/master. >>> >>> >>> >>> Seems like this bug has been introduced when I made the gen5 >>> driver >>> >>> depend >>> >>> on RAM. Unfortunately, all the drivers use one Kconfig item >>> (although >>> >>> these >>> >>> are totally different drivers) but now only gen5 depends on >>> RAM. Is >>> >>> there >>> >>> any Kconfig magic to fix this without duplicating the config >>> item >>> >>> entries? >>> >> >>> >> I think you may want something more like: >>> >> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >>> >> index 04a207c9403e..4a23e327dfb4 100644 >>> >> --- a/arch/arm/Kconfig >>> >> +++ b/arch/arm/Kconfig >>> >> @@ -821,14 +821,12 @@ config ARCH_SOCFPGA >>> >> select DM_SERIAL >>> >> select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || >>> >> TARGET_SOCFPGA_ARRIA10 >>> >> select OF_CONTROL >>> >> - select RAM if TARGET_SOCFPGA_GEN5 >>> >> select SPL_DM_RESET if DM_RESET >>> >> select SPL_DM_SERIAL >>> >> select SPL_LIBCOMMON_SUPPORT >>> >> select SPL_LIBGENERIC_SUPPORT >>> >> select SPL_NAND_SUPPORT if SPL_NAND_DENALI >>> >> select SPL_OF_CONTROL >>> >> - select SPL_RAM if TARGET_SOCFPGA_GEN5 >>> >> select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 >>> >> select SPL_SERIAL_SUPPORT >>> >> select SPL_WATCHDOG_SUPPORT >>> >> diff --git a/drivers/ddr/altera/Kconfig >>> b/drivers/ddr/altera/Kconfig >>> >> index 7370d4133a67..8f60b56eb848 100644 >>> >> --- a/drivers/ddr/altera/Kconfig >>> >> +++ b/drivers/ddr/altera/Kconfig >>> >> @@ -1,6 +1,7 @@ >>> >> config ALTERA_SDRAM >>> >> bool "SoCFPGA DDR SDRAM driver" >>> >> - depends on RAM >>> >> depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 >>> >> + select RAM if TARGET_SOCFPGA_GEN5 >>> >> + select SPL_RAM if TARGET_SOCFPGA_GEN5 >>> >> help >>> >> Enable DDR SDRAM controller for the SoCFPGA devices. >>> >> >>> >> But I didn't test anything other than socfpga_arria10/arria5 as >>> >> building. >>> > >>> > Tom, >>> > Thanks for the hint. I did just that and it works for me >>> (cyclone5). >>> > As only this platform is affected by this patch, it should be >>> fine. >>> > >>> > Marek, >>> > how should we proceed? I pushed the change as suggested by Tom >>> to: >>> > >>> > https://github.com/goldsimon/u-boot.git >>> > >>> > or I could send v5 of the series that broke arria10...? >>> >>> Send me a single patch on top of u-boot-socfpga/master, I'll add >>> it and >>> that should take care of it. It would also make things well >>> documented >>> for other people who run into this. >>> >>> >>> To make it clear, patch 6/12 of this PR is ok for gen5 but breaks >>> arria10. This is not something anyone could run into as it's new. I'd >>> rather fix the patches before merging them to master (keep things >>> bisectable for a10). >>> >>> Unfortunately, I'll be more or less offline until Tuesday. If my github >>> branch isn't enough, I'll send something when I'm back with PC access. >> >> I can squash the patch(es), that's fine. I just need the patch posted to >> the ML. > > Ok, I'm back online. I've just sent the updated patch to fix the build > issue to the ML (see https://patchwork.ozlabs.org/patch/1086623/). This > one is meant as replacement for 82b40a096410 in current > u-boot-socfpga/master. > > Let me know if there's anything else missing. Once this is applied, I'll > prepare a PR for the next batch.
I was hoping for a patch I can squash into the previous one, so the diff would be easily visible. Oh well, applied, let's see what CI has to say now. -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
