On Wed, Mar 27, 2019 at 10:15 AM Ley Foon Tan <ley.foon....@intel.com> wrote: > > Convert Stratix 10 SDRAM driver to device model.
Nice to see that :-) > > Get rid of call to socfpga_per_reset() and use reset > framework. > > SPL is changed from calling function in SDRAM driver > directly to just probing UCLASS_RAM. > > Move sdram_s10.h from arch to driver/ddr/altera directory. > > Signed-off-by: Ley Foon Tan <ley.foon....@intel.com> > --- > arch/arm/Kconfig | 4 +- > arch/arm/dts/socfpga_stratix10.dtsi | 10 + > arch/arm/dts/socfpga_stratix10_socdk.dts | 4 + > arch/arm/mach-socfpga/Kconfig | 1 + > arch/arm/mach-socfpga/spl_s10.c | 9 +- > drivers/ddr/altera/Kconfig | 2 +- > drivers/ddr/altera/sdram_s10.c | 246 ++++++++++++------ > .../mach => drivers/ddr/altera}/sdram_s10.h | 4 - > include/configs/socfpga_stratix10_socdk.h | 5 - > 9 files changed, 195 insertions(+), 90 deletions(-) > rename {arch/arm/mach-socfpga/include/mach => > drivers/ddr/altera}/sdram_s10.h (97%) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 77a534f81fd..a2d4f7f4c25 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -821,14 +821,14 @@ config ARCH_SOCFPGA > select DM_SERIAL > select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || > TARGET_SOCFPGA_ARRIA10 > select OF_CONTROL > - select RAM if TARGET_SOCFPGA_GEN5 > + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 > select SPL_DM_RESET if DM_RESET > select SPL_DM_SERIAL > select SPL_LIBCOMMON_SUPPORT > select SPL_LIBGENERIC_SUPPORT > select SPL_NAND_SUPPORT if SPL_NAND_DENALI > select SPL_OF_CONTROL > - select SPL_RAM if TARGET_SOCFPGA_GEN5 > + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 > select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 > select SPL_SERIAL_SUPPORT > select SPL_WATCHDOG_SUPPORT > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi > b/arch/arm/dts/socfpga_stratix10.dtsi > index ee93725d648..15d0f88f182 100644 > --- a/arch/arm/dts/socfpga_stratix10.dtsi > +++ b/arch/arm/dts/socfpga_stratix10.dtsi > @@ -245,6 +245,16 @@ > u-boot,dm-pre-reloc; > }; > > + sdr: sdr@f8000400 { > + compatible = "altr,sdr-ctl-s10"; > + reg = <0xf8000400 0x80>, > + <0xf8010000 0x190>, > + <0xf8011000 0x500>; > + resets = <&rst DDRSCH_RESET>; > + u-boot,dm-pre-reloc; > + status = "disabled"; Why is this optional? The SPL won't work without that any more by default, or would it? I would have thought it's enabled by default? > + }; > + > spi0: spi@ffda4000 { > compatible = "snps,dw-apb-ssi"; > #address-cells = <1>; > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts > b/arch/arm/dts/socfpga_stratix10_socdk.dts > index c59b77d8298..dcaca77ea69 100644 > --- a/arch/arm/dts/socfpga_stratix10_socdk.dts > +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts > @@ -87,6 +87,10 @@ > smplsel = <0>; > }; > > +&sdr { > + status = "okay"; > +}; > + > &uart0 { > status = "okay"; > }; > diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig > index 441b9d41291..9aa7f062932 100644 > --- a/arch/arm/mach-socfpga/Kconfig > +++ b/arch/arm/mach-socfpga/Kconfig > @@ -38,6 +38,7 @@ config TARGET_SOCFPGA_GEN5 > > config TARGET_SOCFPGA_STRATIX10 > bool > + select ALTERA_SDRAM > select ARMV8_MULTIENTRY > select ARMV8_SET_SMPEN > select ARMV8_PSCI > diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c > index 393c9949d08..9f763b2dd4d 100644 > --- a/arch/arm/mach-socfpga/spl_s10.c > +++ b/arch/arm/mach-socfpga/spl_s10.c > @@ -15,9 +15,9 @@ > #include <asm/arch/firewall_s10.h> > #include <asm/arch/mailbox_s10.h> > #include <asm/arch/reset_manager.h> > -#include <asm/arch/sdram_s10.h> > #include <asm/arch/system_manager.h> > #include <watchdog.h> > +#include <dm/uclass.h> > > DECLARE_GLOBAL_DATA_PTR; > > @@ -119,6 +119,7 @@ void board_init_f(ulong dummy) > { > const struct cm_config *cm_default_cfg = cm_get_default_config(); > int ret; > + struct udevice *dev; > > #ifdef CONFIG_HW_WATCHDOG > /* Ensure watchdog is paused when debugging is happening */ > @@ -178,9 +179,9 @@ void board_init_f(ulong dummy) > clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), > CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); > > - debug("DDR: Initializing Hard Memory Controller\n"); > - if (sdram_mmr_init_full(0)) { > - puts("DDR: Initialization failed.\n"); > + ret = uclass_get_device(UCLASS_RAM, 0, &dev); > + if (ret) { > + debug("DRAM init failed: %d\n", ret); > hang(); > } > > diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig > index 7370d4133a6..a64e406355e 100644 > --- a/drivers/ddr/altera/Kconfig > +++ b/drivers/ddr/altera/Kconfig > @@ -1,6 +1,6 @@ > config ALTERA_SDRAM > bool "SoCFPGA DDR SDRAM driver" > depends on RAM > - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 > + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || > TARGET_SOCFPGA_STRATIX10 > help > Enable DDR SDRAM controller for the SoCFPGA devices. > diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c > index e4d4a02ca2c..d2f32726094 100644 > --- a/drivers/ddr/altera/sdram_s10.c > +++ b/drivers/ddr/altera/sdram_s10.c > @@ -5,17 +5,32 @@ > */ > > #include <common.h> > +#include <dm.h> > #include <errno.h> > #include <div64.h> > #include <fdtdec.h> > -#include <asm/io.h> > +#include <ram.h> > +#include <reset.h> > +#include "sdram_s10.h" > #include <wait_bit.h> > #include <asm/arch/firewall_s10.h> > -#include <asm/arch/sdram_s10.h> > #include <asm/arch/system_manager.h> > #include <asm/arch/reset_manager.h> > +#include <asm/io.h> > #include <linux/sizes.h> > > +#ifdef CONFIG_SPL_BUILD > + > +struct altera_sdram_priv { > + struct ram_info info; > +}; > + > +struct altera_sdram_platdata { > + void __iomem *hmc; > + void __iomem *ddr_sch; > + void __iomem *iomhc; > +}; > + > DECLARE_GLOBAL_DATA_PTR; > > static const struct socfpga_system_manager *sysmgr_regs = > @@ -51,25 +66,26 @@ u32 ddr_config[] = { > DDR_CONFIG(1, 4, 10, 17), > }; > > -static u32 hmc_readl(u32 reg) > +static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) > { > - return readl(((void __iomem *)SOCFPGA_HMC_MMR_IO48_ADDRESS + (reg))); > + return readl(plat->iomhc + (reg)); > } > > -static u32 hmc_ecc_readl(u32 reg) > +static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) > { > - return readl((void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); > + return readl(plat->hmc + (reg)); > } > > -static u32 hmc_ecc_writel(u32 data, u32 reg) > +static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, > + u32 data, u32 reg) > { > - return writel(data, (void __iomem *)SOCFPGA_SDR_ADDRESS + (reg)); > + return writel(data, plat->hmc + (reg)); > } > > -static u32 ddr_sch_writel(u32 data, u32 reg) > +static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, > + u32 reg) > { > - return writel(data, > - (void __iomem *)SOCFPGA_SDR_SCHEDULER_ADDRESS + (reg)); > + return writel(data, plat->ddr_sch + (reg)); > } > > int match_ddr_conf(u32 ddr_conf) > @@ -83,37 +99,38 @@ int match_ddr_conf(u32 ddr_conf) > return 0; > } > > -static int emif_clear(void) > +static int emif_clear(struct altera_sdram_platdata *plat) > { > - hmc_ecc_writel(0, RSTHANDSHAKECTRL); > + hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); > > - return wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + > + return wait_for_bit_le32((const void *)(plat->hmc + > RSTHANDSHAKESTAT), > DDR_HMC_RSTHANDSHAKE_MASK, > false, 1000, false); > } > > -static int emif_reset(void) > +static int emif_reset(struct altera_sdram_platdata *plat) > { > u32 c2s, s2c, ret; > > - c2s = hmc_ecc_readl(RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; > - s2c = hmc_ecc_readl(RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; > + c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & > DDR_HMC_RSTHANDSHAKE_MASK; > + s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & > DDR_HMC_RSTHANDSHAKE_MASK; > > debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", > - c2s, s2c, hmc_readl(NIOSRESERVED0), hmc_readl(NIOSRESERVED1), > - hmc_readl(NIOSRESERVED2), hmc_readl(DRAMSTS)); > + c2s, s2c, hmc_readl(plat, NIOSRESERVED0), > + hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2), > + hmc_readl(plat, DRAMSTS)); > > - if (s2c && emif_clear()) { > + if (s2c && emif_clear(plat)) { > printf("DDR: emif_clear() failed\n"); > return -1; > } > > debug("DDR: Triggerring emif reset\n"); > - hmc_ecc_writel(DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); > + hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); > > /* if seq2core[3] = 0, we are good */ > - ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + > + ret = wait_for_bit_le32((const void *)(plat->hmc + > RSTHANDSHAKESTAT), > DDR_HMC_SEQ2CORE_INT_RESP_MASK, > false, 1000, false); > @@ -122,7 +139,7 @@ static int emif_reset(void) > return ret; > } > > - ret = emif_clear(); > + ret = emif_clear(plat); > if (ret) { > printf("DDR: emif_clear() failed\n"); > return ret; > @@ -240,13 +257,37 @@ static void sdram_size_check(bd_t *bd) > debug("DDR: SDRAM size check passed!\n"); > } > > +/** > + * sdram_calculate_size() - Calculate SDRAM size > + * > + * Calculate SDRAM device size based on SDRAM controller parameters. > + * Size is specified in bytes. > + */ > +static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) > +{ > + u32 dramaddrw = hmc_readl(plat, DRAMADDRW); > + > + phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + > + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + > + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + > + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + > + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); > + > + size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & > + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); > + > + return size; > +} > + > /** > * sdram_mmr_init_full() - Function to initialize SDRAM MMR > * > * Initialize the SDRAM MMR. > */ > -int sdram_mmr_init_full(unsigned int unused) > +static int sdram_mmr_init_full(struct udevice *dev) > { > + struct altera_sdram_platdata *plat = dev->platdata; > + struct altera_sdram_priv *priv = dev_get_priv(dev); > u32 update_value, io48_value, ddrioctl; > u32 i; > int ret; > @@ -303,19 +344,16 @@ int sdram_mmr_init_full(unsigned int unused) > return -1; > } > > - /* release DDR scheduler from reset */ > - socfpga_per_reset(SOCFPGA_RESET(SDR), 0); > - > /* Try 3 times to do a calibration */ > for (i = 0; i < 3; i++) { > - ret = wait_for_bit_le32((const void *)(SOCFPGA_SDR_ADDRESS + > + ret = wait_for_bit_le32((const void *)(plat->hmc + > DDRCALSTAT), > DDR_HMC_DDRCALSTAT_CAL_MSK, true, > 1000, > false); > if (!ret) > break; > > - emif_reset(); > + emif_reset(plat); > } > > if (ret) { > @@ -324,16 +362,16 @@ int sdram_mmr_init_full(unsigned int unused) > } > debug("DDR: Calibration success\n"); > > - u32 ctrlcfg0 = hmc_readl(CTRLCFG0); > - u32 ctrlcfg1 = hmc_readl(CTRLCFG1); > - u32 dramaddrw = hmc_readl(DRAMADDRW); > - u32 dramtim0 = hmc_readl(DRAMTIMING0); > - u32 caltim0 = hmc_readl(CALTIMING0); > - u32 caltim1 = hmc_readl(CALTIMING1); > - u32 caltim2 = hmc_readl(CALTIMING2); > - u32 caltim3 = hmc_readl(CALTIMING3); > - u32 caltim4 = hmc_readl(CALTIMING4); > - u32 caltim9 = hmc_readl(CALTIMING9); > + u32 ctrlcfg0 = hmc_readl(plat, CTRLCFG0); > + u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); > + u32 dramaddrw = hmc_readl(plat, DRAMADDRW); > + u32 dramtim0 = hmc_readl(plat, DRAMTIMING0); > + u32 caltim0 = hmc_readl(plat, CALTIMING0); > + u32 caltim1 = hmc_readl(plat, CALTIMING1); > + u32 caltim2 = hmc_readl(plat, CALTIMING2); > + u32 caltim3 = hmc_readl(plat, CALTIMING3); > + u32 caltim4 = hmc_readl(plat, CALTIMING4); > + u32 caltim9 = hmc_readl(plat, CALTIMING9); > > /* > * Configure the DDR IO size [0xFFCFB008] > @@ -349,12 +387,12 @@ int sdram_mmr_init_full(unsigned int unused) > * bit[9:6] = Minor Release # > * bit[14:10] = Major Release # > */ > - update_value = hmc_readl(NIOSRESERVED0); > - hmc_ecc_writel(((update_value & 0xFF) >> 5), DDRIOCTRL); > - ddrioctl = hmc_ecc_readl(DDRIOCTRL); > + update_value = hmc_readl(plat, NIOSRESERVED0); > + hmc_ecc_writel(plat, ((update_value & 0xFF) >> 5), DDRIOCTRL); > + ddrioctl = hmc_ecc_readl(plat, DDRIOCTRL); > > /* enable HPS interface to HMC */ > - hmc_ecc_writel(DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); > + hmc_ecc_writel(plat, DDR_HMC_HPSINTFCSEL_ENABLE_MASK, HPSINTFCSEL); > > /* Set the DDR Configuration */ > io48_value = DDR_CONFIG(CTRLCFG1_CFG_ADDR_ORDER(ctrlcfg1), > @@ -365,10 +403,10 @@ int sdram_mmr_init_full(unsigned int unused) > > update_value = match_ddr_conf(io48_value); > if (update_value) > - ddr_sch_writel(update_value, DDR_SCH_DDRCONF); > + ddr_sch_writel(plat, update_value, DDR_SCH_DDRCONF); > > /* Configure HMC dramaddrw */ > - hmc_ecc_writel(hmc_readl(DRAMADDRW), DRAMADDRWIDTH); > + hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH); > > /* > * Configure DDR timing > @@ -392,7 +430,7 @@ int sdram_mmr_init_full(unsigned int unused) > CALTIMING0_CFG_ACT_TO_RDWR(caltim0) + > CALTIMING4_CFG_PCH_TO_VALID(caltim4)); > > - ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << > + ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT(caltim0) << > DDR_SCH_DDRTIMING_ACTTOACT_OFF) | > (update_value << DDR_SCH_DDRTIMING_RDTOMISS_OFF) | > (io48_value << DDR_SCH_DDRTIMING_WRTOMISS_OFF) | > @@ -406,12 +444,12 @@ int sdram_mmr_init_full(unsigned int unused) > DDR_SCH_DDRTIMING); > > /* Configure DDR mode [precharge = 0] */ > - ddr_sch_writel(((ddrioctl ? 0 : 1) << > + ddr_sch_writel(plat, ((ddrioctl ? 0 : 1) << > DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF), > DDR_SCH_DDRMODE); > > /* Configure the read latency */ > - ddr_sch_writel((DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + > + ddr_sch_writel(plat, (DRAMTIMING0_CFG_TCL(dramtim0) >> 1) + > DDR_READ_LATENCY_DELAY, > DDR_SCH_READ_LATENCY); > > @@ -419,7 +457,7 @@ int sdram_mmr_init_full(unsigned int unused) > * Configuring timing values concerning activate commands > * [FAWBANK alway 1 because always 4 bank DDR] > */ > - ddr_sch_writel(((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << > + ddr_sch_writel(plat, ((CALTIMING0_CFG_ACT_TO_ACT_DB(caltim0) << > DDR_SCH_ACTIVATE_RRD_OFF) | > (CALTIMING9_CFG_4_ACT_TO_ACT(caltim9) << > DDR_SCH_ACTIVATE_FAW_OFF) | > @@ -431,7 +469,7 @@ int sdram_mmr_init_full(unsigned int unused) > * Configuring timing values concerning device to device data bus > * ownership change > */ > - ddr_sch_writel(((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << > + ddr_sch_writel(plat, ((CALTIMING1_CFG_RD_TO_RD_DC(caltim1) << > DDR_SCH_DEVTODEV_BUSRDTORD_OFF) | > (CALTIMING1_CFG_RD_TO_WR_DC(caltim1) << > DDR_SCH_DEVTODEV_BUSRDTOWR_OFF) | > @@ -440,7 +478,7 @@ int sdram_mmr_init_full(unsigned int unused) > DDR_SCH_DEVTODEV); > > /* assigning the SDRAM size */ > - unsigned long long size = sdram_calculate_size(); > + unsigned long long size = sdram_calculate_size(plat); > /* If the size is invalid, use default Config size */ > if (size <= 0) > hw_size = PHYS_SDRAM_1_SIZE; > @@ -462,18 +500,17 @@ int sdram_mmr_init_full(unsigned int unused) > > /* Enable or disable the SDRAM ECC */ > if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { > - setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, > + setbits_le32(plat->hmc + ECCCTRL1, > (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | > DDR_HMC_ECCCTL_CNT_RST_SET_MSK | > DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); > - clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, > + clrbits_le32(plat->hmc + ECCCTRL1, > (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | > DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); > - setbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, > + setbits_le32(plat->hmc + ECCCTRL2, > (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | > DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); > - writel(DDR_HMC_ERRINTEN_INTMASK, > - SOCFPGA_SDR_ADDRESS + ERRINTENS); > + hmc_ecc_writel(plat, DDR_HMC_ERRINTEN_INTMASK, ERRINTENS); > > /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ > writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); > @@ -482,39 +519,100 @@ int sdram_mmr_init_full(unsigned int unused) > if (!cpu_has_been_warmreset()) > sdram_init_ecc_bits(&bd); > } else { > - clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL1, > + clrbits_le32(plat->hmc + ECCCTRL1, > (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | > DDR_HMC_ECCCTL_CNT_RST_SET_MSK | > DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); > - clrbits_le32(SOCFPGA_SDR_ADDRESS + ECCCTRL2, > + clrbits_le32(plat->hmc + ECCCTRL2, > (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | > DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); > } > > sdram_size_check(&bd); > > + priv->info.base = bd.bi_dram[0].start; > + priv->info.size = gd->ram_size; > + > debug("DDR: HMC init success\n"); > return 0; > } > > -/** > - * sdram_calculate_size() - Calculate SDRAM size > - * > - * Calculate SDRAM device size based on SDRAM controller parameters. > - * Size is specified in bytes. > - */ > -phys_size_t sdram_calculate_size(void) > +static int altera_sdram_ofdata_to_platdata(struct udevice *dev) > { > - u32 dramaddrw = hmc_readl(DRAMADDRW); > + struct altera_sdram_platdata *plat = dev->platdata; > + fdt_addr_t addr; > > - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + > - DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + > - DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + > - DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + > - DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); > + addr = dev_read_addr_index(dev, 0); > + if (addr == FDT_ADDR_T_NONE) > + return -EINVAL; > + plat->ddr_sch = (void __iomem *)addr; > > - size *= (2 << (hmc_ecc_readl(DDRIOCTRL) & > - DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); > + addr = dev_read_addr_index(dev, 1); > + if (addr == FDT_ADDR_T_NONE) > + return -EINVAL; > + plat->iomhc = (void __iomem *)addr; > > - return size; > + addr = dev_read_addr_index(dev, 2); > + if (addr == FDT_ADDR_T_NONE) > + return -EINVAL; > + plat->hmc = (void __iomem *)addr; > + > + return 0; > +} > + > +static int altera_sdram_probe(struct udevice *dev) > +{ > + int ret; > + struct reset_ctl_bulk resets; > + > + ret = reset_get_bulk(dev, &resets); > + if (ret) { > + dev_err(dev, "Can't get reset: %d\n", ret); > + return -ENODEV; > + } > + reset_deassert_bulk(&resets); > + > + if (sdram_mmr_init_full(dev) != 0) { > + puts("SDRAM init failed.\n"); > + goto failed; > + } > + > + return 0; > + > +failed: > + reset_release_bulk(&resets); > + return -ENODEV; > } > + > +static int altera_sdram_get_info(struct udevice *dev, > + struct ram_info *info) > +{ > + struct altera_sdram_priv *priv = dev_get_priv(dev); > + > + info->base = priv->info.base; > + info->size = priv->info.size; > + > + return 0; > +} > + > +static struct ram_ops altera_sdram_ops = { > + .get_info = altera_sdram_get_info, > +}; > + > +static const struct udevice_id altera_sdram_ids[] = { > + { .compatible = "altr,sdr-ctl-s10" }, > + { /* sentinel */ } > +}; > + > +U_BOOT_DRIVER(altera_sdram) = { > + .name = "altr_sdr_ctl", > + .id = UCLASS_RAM, > + .of_match = altera_sdram_ids, > + .ops = &altera_sdram_ops, > + .ofdata_to_platdata = altera_sdram_ofdata_to_platdata, > + .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata), > + .probe = altera_sdram_probe, > + .priv_auto_alloc_size = sizeof(struct altera_sdram_priv), > +}; > + > +#endif /* CONFIG_SPL_BUILD */ > diff --git a/arch/arm/mach-socfpga/include/mach/sdram_s10.h > b/drivers/ddr/altera/sdram_s10.h > similarity index 97% > rename from arch/arm/mach-socfpga/include/mach/sdram_s10.h > rename to drivers/ddr/altera/sdram_s10.h > index f39206ca1ee..096c06cba21 100644 > --- a/arch/arm/mach-socfpga/include/mach/sdram_s10.h > +++ b/drivers/ddr/altera/sdram_s10.h > @@ -7,10 +7,6 @@ > #ifndef _SDRAM_S10_H_ > #define _SDRAM_S10_H_ > > -phys_size_t sdram_calculate_size(void); > -int sdram_mmr_init_full(unsigned int sdr_phy_reg); > -int sdram_calibration_full(void); > - > #define DDR_TWR 15 > #define DDR_READ_LATENCY_DELAY 40 > #define DDR_ACTIVATE_FAWBANK 0x1 > diff --git a/include/configs/socfpga_stratix10_socdk.h > b/include/configs/socfpga_stratix10_socdk.h > index c68a73ceaeb..8e7c808ce7f 100644 > --- a/include/configs/socfpga_stratix10_socdk.h > +++ b/include/configs/socfpga_stratix10_socdk.h > @@ -139,11 +139,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void); > #define CONFIG_SYS_MEMTEST_START 0 > #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 > > -/* > - * SDRAM controller > - */ > -#define CONFIG_ALTERA_SDRAM > - > /* > * Serial / UART configurations > */ > -- > 2.19.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot