On Wed, 2019-03-06 at 22:05 +0100, Marek Vasut wrote:
> The bootrom seems to leave the D-cache in messed up state, make sure
> the SPL disables it so it can not interfere with operation.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Chin Liang See <chin.liang....@intel.com>
> Cc: Dinh Nguyen <dingu...@kernel.org>
> Cc: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
> Cc: Tien Fong Chee <tien.fong.c...@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.c...@intel.com>
> ---
> arch/arm/mach-socfpga/spl_a10.c | 2 ++
> include/configs/socfpga_arria10_socdk.h | 2 --
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-
> socfpga/spl_a10.c
> index c97eacb424..c8e73d47c0 100644
> --- a/arch/arm/mach-socfpga/spl_a10.c
> +++ b/arch/arm/mach-socfpga/spl_a10.c
> @@ -77,6 +77,8 @@ void spl_board_init(void)
>
> void board_init_f(ulong dummy)
> {
> + dcache_disable();
> +
> socfpga_init_security_policies();
> socfpga_sdram_remap_zero();
>
> diff --git a/include/configs/socfpga_arria10_socdk.h
> b/include/configs/socfpga_arria10_socdk.h
> index 58e446b60a..0f116fbf2d 100644
> --- a/include/configs/socfpga_arria10_socdk.h
> +++ b/include/configs/socfpga_arria10_socdk.h
> @@ -15,8 +15,6 @@
> /*
> * U-Boot general configurations
> */
> -/* Cache options */
> -#define CONFIG_SYS_DCACHE_OFF
>
> /* Memory configurations */
> #define PHYS_SDRAM_1_SIZE 0x40000000
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