On 27. 02. 19 7:10, Chee, Tien Fong wrote: > On Tue, 2019-02-26 at 16:43 +0100, Michal Simek wrote: >> On 26. 02. 19 15:30, Chee, Tien Fong wrote: >>> >>> On Tue, 2019-02-26 at 15:07 +0100, Michal Simek wrote: >>>> >>>> On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote: >>>>> >>>>> >>>>> From: Tien Fong Chee <tien.fong.c...@intel.com> >>>>> >>>>> Add default fitImage file bundling FPGA bitstreams for Arria10. >>>>> >>>>> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> >>>>> >>>>> --- >>>>> >>>>> changes for v8 >>>>> - Reordered the images and fpga configurations. >>>>> - Removed the load property at core image. >>>>> >>>>> changes for v8 >>>>> - Changed the FPGA node name to fpga-core and fpga-periph for >>>>> both >>>>> core and >>>>> periph bitstreams respectively. >>>>> --- >>>>> board/altera/arria10-socdk/fit_spl_fpga.its | 38 >>>>> +++++++++++++++++++++++++++++ >>>>> 1 file changed, 38 insertions(+) >>>>> create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its >>>>> >>>>> diff --git a/board/altera/arria10-socdk/fit_spl_fpga.its >>>>> b/board/altera/arria10-socdk/fit_spl_fpga.its >>>>> new file mode 100644 >>>>> index 0000000..df84562 >>>>> --- /dev/null >>>>> +++ b/board/altera/arria10-socdk/fit_spl_fpga.its >>>>> @@ -0,0 +1,38 @@ >>>>> +// SPDX-License-Identifier: GPL-2.0 >>>>> + /* >>>>> + * Copyright (C) 2019 Intel Corporation <www.intel.com> >>>>> + * >>>>> + */ >>>>> + >>>>> +/dts-v1/; >>>>> + >>>>> +/ { >>>>> + description = "FIT image with FPGA bistream"; >>>>> + #address-cells = <1>; >>>>> + >>>>> + images { >>>>> + fpga-periph@1 { >>>> Still this is DT and using @1 without reg property below is >>>> wrong. >>> Sorry, i'm not getting you. >>> Mind to explain more? >> it should be just fpga-periph { >> because you don't have reg properly below. > So this rule also apply for ITS image node name?
yep. > How about fpga-periph-1? Not a problem with it. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
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