Add the implementation for the CLK_GATE_SETCLR_INV and
CLK_GATE_NO_SETCLR flags.
Signed-off-by: Fabien Parent <fpar...@baylibre.com>
Acked-by: Ryder Lee <ryder....@mediatek.com>
---
v2:
* Add missing support for SETCLR_INV in the mtk_clk_gate_disable func
* Add support for CLK_GATE_NO_SETCLR
---
drivers/clk/mediatek/clk-mtk.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 870b14ed8b..6c6b500d9b 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -390,6 +390,12 @@ static int mtk_clk_gate_enable(struct clk *clk)
case CLK_GATE_SETCLR:
writel(bit, priv->base + gate->regs->clr_ofs);
break;
+ case CLK_GATE_SETCLR_INV:
+ writel(bit, priv->base + gate->regs->set_ofs);
+ break;
+ case CLK_GATE_NO_SETCLR:
+ clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
+ break;
case CLK_GATE_NO_SETCLR_INV:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
break;
@@ -411,6 +417,12 @@ static int mtk_clk_gate_disable(struct clk *clk)
case CLK_GATE_SETCLR:
writel(bit, priv->base + gate->regs->set_ofs);
break;
+ case CLK_GATE_SETCLR_INV:
+ writel(bit, priv->base + gate->regs->clr_ofs);
+ break;
+ case CLK_GATE_NO_SETCLR:
+ clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, bit);
+ break;
case CLK_GATE_NO_SETCLR_INV:
clrsetbits_le32(priv->base + gate->regs->sta_ofs, bit, 0);
break;
--
2.20.1
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