On Thu, Feb 21, 2019 at 10:25 AM Marek Vasut <ma...@denx.de> wrote:
>
> On SoCFPGA Gen5 systems, it can rarely happen that a reboot from Linux
> will result in stale data in PL310 L2 cache controller. Even if the L2
> cache controller is disabled via the CTRL register CTRL_EN bit, those
> data can interfere with operation of devices using DMA, like e.g. the
> DWMMC controller. This can in turn cause e.g. SPL to fail reading data
> from SD/MMC.
>
> The obvious solution here would be to fully reset the L2 cache controller
> via the reset manager MPUMODRST L2 bit, however this causes bus hang even
> if executed entirely from L1 I-cache to avoid generating any bus traffic
> through the L2 cache controller.
>
> This patch thus configures and enables the L2 cache controller very early
> in the SPL boot process, clears the L2 cache and disables the L2 cache
> controller again.
>
> The reason for doing it in SPL is because we need to avoid accessing any
> of the potentially stale data in the L2 cache, and we are certain any of
> the stale data will be below the OCRAM address range. To further reduce
> bus traffic during the L2 cache invalidation, we enable L1 I-cache and
> run the invalidation code entirely out of the L1 I-cache.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Dalon Westergreen <dwest...@gmail.com>
> Cc: Dinh Nguyen <dingu...@kernel.org>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
Tested on socfpga_socrates_defconfig:
Tested-by: Simon Goldschmidt <simon.k.r.goldschm...@gmail.com>
> ---
> V2: Add missing pl310 header
> ---
> arch/arm/mach-socfpga/spl_gen5.c | 58 ++++++++++++++++++++++++++++++++
> 1 file changed, 58 insertions(+)
>
> diff --git a/arch/arm/mach-socfpga/spl_gen5.c
> b/arch/arm/mach-socfpga/spl_gen5.c
> index ccdc661d05..e7b13c4c70 100644
> --- a/arch/arm/mach-socfpga/spl_gen5.c
> +++ b/arch/arm/mach-socfpga/spl_gen5.c
> @@ -5,6 +5,7 @@
>
> #include <common.h>
> #include <asm/io.h>
> +#include <asm/pl310.h>
> #include <asm/u-boot.h>
> #include <asm/utils.h>
> #include <image.h>
> @@ -23,6 +24,8 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> +static struct pl310_regs *const pl310 =
> + (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
> static const struct socfpga_system_manager *sysmgr_regs =
> (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
>
> @@ -63,6 +66,60 @@ u32 spl_boot_mode(const u32 boot_device)
> }
> #endif
>
> +static void socfpga_pl310_clear(void)
> +{
> + u32 mask = 0xff, ena = 0;
> +
> + icache_enable();
> +
> + /* Disable the L2 cache */
> + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> +
> + writel(0x111, &pl310->pl310_tag_latency_ctrl);
> + writel(0x121, &pl310->pl310_data_latency_ctrl);
> +
> + /* enable BRESP, instruction and data prefetch, full line of zeroes */
> + setbits_le32(&pl310->pl310_aux_ctrl,
> + L310_AUX_CTRL_DATA_PREFETCH_MASK |
> + L310_AUX_CTRL_INST_PREFETCH_MASK |
> + L310_SHARED_ATT_OVERRIDE_ENABLE);
> +
> + /* Enable the L2 cache */
> + ena = readl(&pl310->pl310_ctrl);
> + ena |= L2X0_CTRL_EN;
> +
> + /*
> + * Invalidate the PL310 L2 cache. Keep the invalidation code
> + * entirely in L1 I-cache to avoid any bus traffic through
> + * the L2.
> + */
> + asm volatile(
> + ".align 5 \n"
> + " b 3f \n"
> + "1: str %1, [%4] \n"
> + " dsb \n"
> + " isb \n"
> + " str %0, [%2] \n"
> + " dsb \n"
> + " isb \n"
> + "2: ldr %0, [%2] \n"
> + " cmp %0, #0 \n"
> + " bne 2b \n"
> + " str %0, [%3] \n"
> + " dsb \n"
> + " isb \n"
> + " b 4f \n"
> + "3: b 1b \n"
> + "4: nop \n"
> + : "+r"(mask), "+r"(ena)
> + : "r"(&pl310->pl310_inv_way),
> + "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
> + : "memory", "cc");
> +
> + /* Disable the L2 cache */
> + clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
> +}
> +
> void board_init_f(ulong dummy)
> {
> const struct cm_config *cm_default_cfg = cm_get_default_config();
> @@ -85,6 +142,7 @@ void board_init_f(ulong dummy)
> memset(__bss_start, 0, __bss_end - __bss_start);
>
> socfpga_sdram_remap_zero();
> + socfpga_pl310_clear();
>
> debug("Freezing all I/O banks\n");
> /* freeze all IO banks */
> --
> 2.19.2
>
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