On 11.02.19 02:19, Chris Packham wrote:
MV_DDR_FREQ_SAR lets the DDR frequency be determined by hardware strapping. This also has the side effect of running the DDR clock in synchronous mode with the CPU core clock rather than from an independent PLL. We've seen this improve reliability in operation across a number of boards and temperature ranges.Signed-off-by: Chris Packham <judge.pack...@gmail.com> --- board/alliedtelesis/x530/x530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/board/alliedtelesis/x530/x530.c b/board/alliedtelesis/x530/x530.c index b34ae5134547..d7d1942fe686 100644 --- a/board/alliedtelesis/x530/x530.c +++ b/board/alliedtelesis/x530/x530.c @@ -57,7 +57,7 @@ static struct mv_ddr_topology_map board_topology_map = { SPEED_BIN_DDR_1866M, /* speed_bin */ MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ MV_DDR_DIE_CAP_4GBIT, /* die capacity */ - MV_DDR_FREQ_933, /* frequency */ + MV_DDR_FREQ_SAR, /* frequency */ 0, 0, /* cas_l cas_wl */ MV_DDR_TEMP_LOW, /* temperature */ MV_DDR_TIM_2T} }, /* timing */
Reviewed-by: Stefan Roese <s...@denx.de> Thanks, Stefan _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
