On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
> From: Tien Fong Chee <tien.fong.c...@intel.com>
>
> Add FPGA driver to support program FPGA with FPGA bitstream loading from
> filesystem. The driver are designed based on generic firmware loader
> framework. The driver can handle FPGA program operation from loading FPGA
> bitstream in flash to memory and then to program FPGA.
>
> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
>
> ---
>
> changes for v7
> - Restructure the FPGA driver to support both peripheral bitstream and core
> bitstream bundled into FIT image.
> - Support loadable property for core bitstream. User can set loadable
> in DDR for better performance. This loading would be done in one large
> chunk instead of chunk by chunk loading with small memory buffer.
> ---
> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 +
> .../include/mach/fpga_manager_arria10.h | 39 +-
> drivers/fpga/socfpga_arria10.c | 417
> ++++++++++++++++++++-
> 3 files changed, 457 insertions(+), 17 deletions(-)
>
> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> index 998d811..dc55618 100644
> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
> @@ -18,6 +18,24 @@
> /dts-v1/;
> #include "socfpga_arria10_socdk.dtsi"
>
> +/ {
> + chosen {
> + firmware-loader = &fs_loader0;
Shouldn't this be <&fs_loader0>; ?
How did this even pass the DTC ?
> + };
> +
> + fs_loader0: fs-loader@0 {
> + u-boot,dm-pre-reloc;
> + compatible = "u-boot,fs-loader";
> + phandlepart = <&mmc 1>;
> + };
> +};
> +
> +&fpga_mgr {
> + u-boot,dm-pre-reloc;
> + altr,bitstream = "fit_spl_fpga.itb";
> + altr,bitstream-core = "fit_spl_fpga.itb";
> +};
> +
> &mmc {
> u-boot,dm-pre-reloc;
> status = "okay";
> diff --git a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> index 09d13f6..683c84c 100644
> --- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> +++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
> @@ -1,9 +1,13 @@
> /* SPDX-License-Identifier: GPL-2.0 */
> /*
> - * Copyright (C) 2017 Intel Corporation <www.intel.com>
> + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
> * All rights reserved.
> */
>
> +#include <asm/cache.h>
> +#include <altera.h>
> +#include <image.h>
> +
> #ifndef _FPGA_MANAGER_ARRIA10_H_
> #define _FPGA_MANAGER_ARRIA10_H_
>
> @@ -51,6 +55,10 @@
> #define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK BIT(24)
> #define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
>
> +#define FPGA_SOCFPGA_A10_RBF_UNENCRYPTED 0xa65c
> +#define FPGA_SOCFPGA_A10_RBF_ENCRYPTED 0xa65d
> +#define FPGA_SOCFPGA_A10_RBF_PERIPH 0x0001
> +#define FPGA_SOCFPGA_A10_RBF_CORE 0x8001
> #ifndef __ASSEMBLY__
>
> struct socfpga_fpga_manager {
> @@ -88,12 +96,39 @@ struct socfpga_fpga_manager {
> u32 imgcfg_fifo_status;
> };
>
> +enum rbf_type {
> + unknown,
> + periph_section,
> + core_section
> +};
[...]
--
Best regards,
Marek Vasut
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