i.MX8MQ and i.MX8MM has totally different pll design, so
rename clock to clock_imx8mq, then we will add clock_imx8mm.
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/mach-imx/imx8m/Makefile | 3 +-
.../arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0
include/dt-bindings/clock/imx8mm-clock.h | 168 ++++++++++-----------
3 files changed, 86 insertions(+), 85 deletions(-)
rename arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} (100%)
diff --git a/arch/arm/mach-imx/imx8m/Makefile b/arch/arm/mach-imx/imx8m/Makefile
index feff4941c1..42a1544c6b 100644
--- a/arch/arm/mach-imx/imx8m/Makefile
+++ b/arch/arm/mach-imx/imx8m/Makefile
@@ -3,4 +3,5 @@
# Copyright 2017 NXP
obj-y += lowlevel_init.o
-obj-y += clock.o clock_slice.o soc.o
+obj-y += clock_slice.o soc.o
+obj-$(CONFIG_IMX8MQ) += clock_imx8mq.o
diff --git a/arch/arm/mach-imx/imx8m/clock.c
b/arch/arm/mach-imx/imx8m/clock_imx8mq.c
similarity index 100%
rename from arch/arm/mach-imx/imx8m/clock.c
rename to arch/arm/mach-imx/imx8m/clock_imx8mq.c
diff --git a/include/dt-bindings/clock/imx8mm-clock.h
b/include/dt-bindings/clock/imx8mm-clock.h
index d093a87c6f..bb0bf43f71 100644
--- a/include/dt-bindings/clock/imx8mm-clock.h
+++ b/include/dt-bindings/clock/imx8mm-clock.h
@@ -28,44 +28,44 @@
#define IMX8MM_AUDIO_PLL2 19
#define IMX8MM_VIDEO_PLL1 20
#define IMX8MM_DRAM_PLL 21
-#define IMX8MM_GPU_PLL 22
-#define IMX8MM_VPU_PLL 23
-#define IMX8MM_ARM_PLL 24
-#define IMX8MM_SYS_PLL1 25
-#define IMX8MM_SYS_PLL2 26
-#define IMX8MM_SYS_PLL3 27
-#define IMX8MM_AUDIO_PLL1_BYPASS 28
-#define IMX8MM_AUDIO_PLL2_BYPASS 29
+#define IMX8MM_GPU_PLL 22
+#define IMX8MM_VPU_PLL 23
+#define IMX8MM_ARM_PLL 24
+#define IMX8MM_SYS_PLL1 25
+#define IMX8MM_SYS_PLL2 26
+#define IMX8MM_SYS_PLL3 27
+#define IMX8MM_AUDIO_PLL1_BYPASS 28
+#define IMX8MM_AUDIO_PLL2_BYPASS 29
#define IMX8MM_VIDEO_PLL1_BYPASS 30
-#define IMX8MM_DRAM_PLL_BYPASS 31
-#define IMX8MM_GPU_PLL_BYPASS 32
-#define IMX8MM_VPU_PLL_BYPASS 33
-#define IMX8MM_ARM_PLL_BYPASS 34
-#define IMX8MM_SYS_PLL1_BYPASS 35
-#define IMX8MM_SYS_PLL2_BYPASS 36
-#define IMX8MM_SYS_PLL3_BYPASS 37
-#define IMX8MM_AUDIO_PLL1_OUT 38
-#define IMX8MM_AUDIO_PLL2_OUT 39
+#define IMX8MM_DRAM_PLL_BYPASS 31
+#define IMX8MM_GPU_PLL_BYPASS 32
+#define IMX8MM_VPU_PLL_BYPASS 33
+#define IMX8MM_ARM_PLL_BYPASS 34
+#define IMX8MM_SYS_PLL1_BYPASS 35
+#define IMX8MM_SYS_PLL2_BYPASS 36
+#define IMX8MM_SYS_PLL3_BYPASS 37
+#define IMX8MM_AUDIO_PLL1_OUT 38
+#define IMX8MM_AUDIO_PLL2_OUT 39
#define IMX8MM_VIDEO_PLL1_OUT 40
-#define IMX8MM_DRAM_PLL_OUT 41
-#define IMX8MM_GPU_PLL_OUT 42
-#define IMX8MM_VPU_PLL_OUT 43
-#define IMX8MM_ARM_PLL_OUT 44
-#define IMX8MM_SYS_PLL1_OUT 45
-#define IMX8MM_SYS_PLL2_OUT 46
-#define IMX8MM_SYS_PLL3_OUT 47
-#define IMX8MM_SYS_PLL1_40M 48
-#define IMX8MM_SYS_PLL1_80M 49
+#define IMX8MM_DRAM_PLL_OUT 41
+#define IMX8MM_GPU_PLL_OUT 42
+#define IMX8MM_VPU_PLL_OUT 43
+#define IMX8MM_ARM_PLL_OUT 44
+#define IMX8MM_SYS_PLL1_OUT 45
+#define IMX8MM_SYS_PLL2_OUT 46
+#define IMX8MM_SYS_PLL3_OUT 47
+#define IMX8MM_SYS_PLL1_40M 48
+#define IMX8MM_SYS_PLL1_80M 49
#define IMX8MM_SYS_PLL1_100M 50
-#define IMX8MM_SYS_PLL1_133M 51
-#define IMX8MM_SYS_PLL1_160M 52
-#define IMX8MM_SYS_PLL1_200M 53
-#define IMX8MM_SYS_PLL1_266M 54
-#define IMX8MM_SYS_PLL1_400M 55
-#define IMX8MM_SYS_PLL1_800M 56
-#define IMX8MM_SYS_PLL2_50M 57
-#define IMX8MM_SYS_PLL2_100M 58
-#define IMX8MM_SYS_PLL2_125M 59
+#define IMX8MM_SYS_PLL1_133M 51
+#define IMX8MM_SYS_PLL1_160M 52
+#define IMX8MM_SYS_PLL1_200M 53
+#define IMX8MM_SYS_PLL1_266M 54
+#define IMX8MM_SYS_PLL1_400M 55
+#define IMX8MM_SYS_PLL1_800M 56
+#define IMX8MM_SYS_PLL2_50M 57
+#define IMX8MM_SYS_PLL2_100M 58
+#define IMX8MM_SYS_PLL2_125M 59
#define IMX8MM_SYS_PLL2_166M 60
#define IMX8MM_SYS_PLL2_200M 61
#define IMX8MM_SYS_PLL2_250M 62
@@ -77,59 +77,59 @@
#define IMX8MM_CLK_VPU_SRC 68
#define IMX8MM_CLK_GPU3D_SRC 69
#define IMX8MM_CLK_GPU2D_SRC 70
-#define IMX8MM_CLK_A53_CG 71
-#define IMX8MM_CLK_M4_CG 72
-#define IMX8MM_CLK_VPU_CG 73
-#define IMX8MM_CLK_GPU3D_CG 74
-#define IMX8MM_CLK_GPU2D_CG 75
-#define IMX8MM_CLK_A53_DIV 76
-#define IMX8MM_CLK_M4_DIV 77
-#define IMX8MM_CLK_VPU_DIV 78
-#define IMX8MM_CLK_GPU3D_DIV 79
+#define IMX8MM_CLK_A53_CG 71
+#define IMX8MM_CLK_M4_CG 72
+#define IMX8MM_CLK_VPU_CG 73
+#define IMX8MM_CLK_GPU3D_CG 74
+#define IMX8MM_CLK_GPU2D_CG 75
+#define IMX8MM_CLK_A53_DIV 76
+#define IMX8MM_CLK_M4_DIV 77
+#define IMX8MM_CLK_VPU_DIV 78
+#define IMX8MM_CLK_GPU3D_DIV 79
#define IMX8MM_CLK_GPU2D_DIV 80
#define IMX8MM_CLK_MAIN_AXI_SRC 81
-#define IMX8MM_CLK_ENET_AXI_SRC 82
-#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
-#define IMX8MM_CLK_VPU_BUS_SRC 84
-#define IMX8MM_CLK_DISP_AXI_SRC 85
-#define IMX8MM_CLK_DISP_APB_SRC 86
-#define IMX8MM_CLK_DISP_RTRM_SRC 87
-#define IMX8MM_CLK_USB_BUS_SRC 88
-#define IMX8MM_CLK_GPU_AXI_SRC 89
+#define IMX8MM_CLK_ENET_AXI_SRC 82
+#define IMX8MM_CLK_NAND_USDHC_BUS_SRC 83
+#define IMX8MM_CLK_VPU_BUS_SRC 84
+#define IMX8MM_CLK_DISP_AXI_SRC 85
+#define IMX8MM_CLK_DISP_APB_SRC 86
+#define IMX8MM_CLK_DISP_RTRM_SRC 87
+#define IMX8MM_CLK_USB_BUS_SRC 88
+#define IMX8MM_CLK_GPU_AXI_SRC 89
#define IMX8MM_CLK_GPU_AHB_SRC 90
-#define IMX8MM_CLK_NOC_SRC 91
-#define IMX8MM_CLK_NOC_APB_SRC 92
-#define IMX8MM_CLK_MAIN_AXI_CG 93
-#define IMX8MM_CLK_ENET_AXI_CG 94
-#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
-#define IMX8MM_CLK_VPU_BUS_CG 96
-#define IMX8MM_CLK_DISP_AXI_CG 97
-#define IMX8MM_CLK_DISP_APB_CG 98
-#define IMX8MM_CLK_DISP_RTRM_CG 99
+#define IMX8MM_CLK_NOC_SRC 91
+#define IMX8MM_CLK_NOC_APB_SRC 92
+#define IMX8MM_CLK_MAIN_AXI_CG 93
+#define IMX8MM_CLK_ENET_AXI_CG 94
+#define IMX8MM_CLK_NAND_USDHC_BUS_CG 95
+#define IMX8MM_CLK_VPU_BUS_CG 96
+#define IMX8MM_CLK_DISP_AXI_CG 97
+#define IMX8MM_CLK_DISP_APB_CG 98
+#define IMX8MM_CLK_DISP_RTRM_CG 99
#define IMX8MM_CLK_USB_BUS_CG 100
-#define IMX8MM_CLK_GPU_AXI_CG 101
-#define IMX8MM_CLK_GPU_AHB_CG 102
-#define IMX8MM_CLK_NOC_CG 103
-#define IMX8MM_CLK_NOC_APB_CG 104
-#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
-#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
-#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
-#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
-#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
-#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
-#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
-#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
-#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
-#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
-#define IMX8MM_CLK_NOC_PRE_DIV 115
-#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
-#define IMX8MM_CLK_MAIN_AXI_DIV 117
-#define IMX8MM_CLK_ENET_AXI_DIV 118
-#define IMX8MM_CLK_NAND_USDHC_BUS 119
-#define IMX8MM_CLK_VPU_BUS_DIV 120
-#define IMX8MM_CLK_DISP_AXI_DIV 121
-#define IMX8MM_CLK_DISP_APB_DIV 122
-#define IMX8MM_CLK_DISP_RTRM_DIV 123
+#define IMX8MM_CLK_GPU_AXI_CG 101
+#define IMX8MM_CLK_GPU_AHB_CG 102
+#define IMX8MM_CLK_NOC_CG 103
+#define IMX8MM_CLK_NOC_APB_CG 104
+#define IMX8MM_CLK_MAIN_AXI_PRE_DIV 105
+#define IMX8MM_CLK_ENET_AXI_PRE_DIV 106
+#define IMX8MM_CLK_NAND_USDHC_BUS_PRE_DIV 107
+#define IMX8MM_CLK_VPU_BUS_PRE_DIV 108
+#define IMX8MM_CLK_DISP_AXI_PRE_DIV 109
+#define IMX8MM_CLK_DISP_APB_PRE_DIV 110
+#define IMX8MM_CLK_DISP_RTRM_PRE_DIV 111
+#define IMX8MM_CLK_USB_BUS_PRE_DIV 112
+#define IMX8MM_CLK_GPU_AXI_PRE_DIV 113
+#define IMX8MM_CLK_GPU_AHB_PRE_DIV 114
+#define IMX8MM_CLK_NOC_PRE_DIV 115
+#define IMX8MM_CLK_NOC_APB_PRE_DIV 116
+#define IMX8MM_CLK_MAIN_AXI_DIV 117
+#define IMX8MM_CLK_ENET_AXI_DIV 118
+#define IMX8MM_CLK_NAND_USDHC_BUS 119
+#define IMX8MM_CLK_VPU_BUS_DIV 120
+#define IMX8MM_CLK_DISP_AXI_DIV 121
+#define IMX8MM_CLK_DISP_APB_DIV 122
+#define IMX8MM_CLK_DISP_RTRM_DIV 123
#define IMX8MM_CLK_USB_BUS_DIV 124
#define IMX8MM_CLK_GPU_AXI_DIV 125
#define IMX8MM_CLK_GPU_AHB_DIV 126
--
2.14.1
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