On 01/22/2019 05:53 AM, Simon Glass wrote: > We use every second block when creating a SPI image, so update the text to > say this explicitly. > > Signed-off-by: Simon Glass <s...@chromium.org> > --- > > Changes in v2: None > > doc/README.rockchip | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/doc/README.rockchip b/doc/README.rockchip > index 9542265a83..db5724e073 100644 > --- a/doc/README.rockchip > +++ b/doc/README.rockchip > @@ -262,7 +262,7 @@ To write an image that boots from SPI flash (e.g. for the > Haier Chromebook): > dd if=out.bin of=out.bin.pad bs=4M conv=sync > > This converts the SPL image to the required SPI format by adding the Rockchip > -header and skipping every 2KB block. Then the U-Boot image is written at > +header and skipping every second 2KB block. Then the U-Boot image is written > at
For some of latest SoCs, the SPI image do not have this limitation, and can re-use the SD image, well, let me update this part once I get the detail list. Reviewed-by: Kever Yang <kever.y...@rock-chips.com> Thanks, - Kever > offset 128KB and the whole image is padded to 4MB which is the SPI flash > size. > The position of U-Boot is controlled with this setting in U-Boot: > _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
