Hi Lukasz,
On Sat, Jan 19, 2019 at 7:15 AM Lukasz Majewski <lu...@denx.de> wrote:
> +static ulong imx6q_clk_get_rate(struct clk *clk)
> +{
> + ulong rate = 0;
> +
> + debug("%s(#%lu)\n", __func__, clk->id);
> +
> + switch (clk->id) {
> + case IMX6QDL_CLK_ECSPI1:
> + case IMX6QDL_CLK_ECSPI2:
> + case IMX6QDL_CLK_ECSPI3:
> + case IMX6QDL_CLK_ECSPI4:
> + return imx6_get_cspi_clk();
> +
> + case IMX6QDL_CLK_USDHC1:
> + case IMX6QDL_CLK_USDHC2:
> + case IMX6QDL_CLK_USDHC3:
> + case IMX6QDL_CLK_USDHC4:
> + return imx6_get_usdhc_clk(clk->id - IMX6QDL_CLK_USDHC1);
I don't think this scales well as this needs to grow for all other
peripherals and for each port instance.
If we are adding a clock driver for mx6, why don't we add it just like
the kernel one?
Barebox imports the clock driver from the kernel and it is much cleaner:
https://git.pengutronix.de/cgit/barebox/tree/drivers/clk/imx/clk-imx6.c
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