> -----Original Message----- > From: Alexander Graf [mailto:ag...@suse.de] > Sent: Friday, January 18, 2019 4:39 AM > To: Anup Patel <anup.pa...@wdc.com>; Rick Chen <r...@andestech.com>; > Bin Meng <bmeng...@gmail.com>; Joe Hershberger > <joe.hershber...@ni.com>; Lukas Auer <lukas.a...@aisec.fraunhofer.de>; > Masahiro Yamada <yamada.masah...@socionext.com>; Simon Glass > <s...@chromium.org> > Cc: Palmer Dabbelt <pal...@sifive.com>; Paul Walmsley > <paul.walms...@sifive.com>; Atish Patra <atish.pa...@wdc.com>; > Christoph Hellwig <h...@infradead.org>; U-Boot Mailing List <u- > b...@lists.denx.de> > Subject: Re: [PATCH 00/11] SiFive FU540 Support > > > > On 17.01.19 11:38, Anup Patel wrote: > > This patchset adds SiFive Freedom Unleashed (FU540) support to RISC-V > > U-Boot. > > > > The patches are based upon latest RISC-V U-Boot tree > > (git://git.denx.de/u-boot-riscv.git) at commit id > > 91882c472d8c0aef4db699d3f2de55bf43d4ae4b > > > > All drivers namely: SiFive PRCI, SiFive Serial, and Cadance MACB > > Ethernet work fine on actual SiFive Unleashed board and QEMU sifive_u > > machine. > > Great job, looks very clean to me!
Thanks. > > Slight nitpick on the SoB lines though. Usually your SoB should always come > at the end if it went through your fingers last. > > I saw a few patches where Atish was either the sole person in SoB or is listed > after you in the SoB order. This is slightly incorrect, as you as the sender > of > the patch set should always occur at the end of the SoB list. Sure, I will fix ordering of SoB > > Thanks a lot for cooking up this patch set, I'm looking very much forward to a > world where running new kernels is easy on RISC-V :). Regards, Anup _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
