Hi,
----- Siarhei Siamashka <siarhei.siamas...@gmail.com> a écrit :
> On Wed, 2 Jan 2019 14:31:41 +0100
> Guillaume GARDET <guillaume.gar...@free.fr> wrote:
>
> > Building peach-pi smdk5420 and peach-pit with thumb mode for SPL
> > ends-up in the following error:
> >
> > Error: Thumb encoding does not support an immediate here -- `msr
> > cpsr_c,#0x13|0xC0'
> >
> > Use an intermediate register to be able to use thumb for exynos5 SPL.
> >
> >
> > Signed-off-by: Guillaume GARDET <guillaume.gar...@free.fr>
> >
> > Cc: Albert Aribaud <albert.u.b...@aribaud.net>
> > Cc: Minkyu Kang <mk7.k...@samsung.com>
> > Cc: Tom Rini <tr...@konsulko.com>
> >
> > ---
> > arch/arm/mach-exynos/include/mach/system.h | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm/mach-exynos/include/mach/system.h
> > b/arch/arm/mach-exynos/include/mach/system.h
> > index 4837781957..81fa9800b4 100644
> > --- a/arch/arm/mach-exynos/include/mach/system.h
> > +++ b/arch/arm/mach-exynos/include/mach/system.h
> > @@ -58,7 +58,8 @@ struct exynos5_sysreg {
> > /* Move 0xd3 value to CPSR register to enable SVC mode */
> > #define svc32_mode_en() __asm__ __volatile__
> > \
> > ("@ I&F disable, Mode: 0x13 - SVC\n\t" \
> > - "msr cpsr_c, #0x13|0xC0\n\t" : : )
> > + "mov r0, #0x13|0xC0\n\t" \
> > + "msr cpsr_c, r0\n\t" : : )
>
> This line needs "r0" to be also added to the clobber list. If you
> don't do this, then you may encounter sporadic r0 corruption
> problem depending on the compiler version or optimization settings.
>
> This would be:
>
> "msr cpsr_c, r0\n\t" : : : "r0")
>
> See https://gcc.gnu.org/onlinedocs/gcc/Extended-Asm.html for more
> details.
>
> An even better option is to just use something like this and give
> the compiler freedom to pick any register:
>
> "msr cpsr_c, %0\n\t" : : "r"(0x13|0xC0))
Thanks for the report Siarhei.
Minkyu, please merge also this patch:
https://lists.denx.de/pipermail/u-boot/2019-January/353533.html
Thanks,
Guillaume
>
> --
> Best regards,
> Siarhei Siamashka
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