On 13. 12. 18 14:37, Bin Meng wrote: > Hi Stefan, > > On Thu, Dec 13, 2018 at 9:26 PM Stefan Theil <stefan.th...@mixed-mode.de> > wrote: >> >> Hmm good question. I went with flush because that's what's done in the >> transmit function: >> >> addr = (ulong) ptr; >> addr &= ~(ARCH_DMA_MINALIGN - 1); >> size = roundup(len, ARCH_DMA_MINALIGN); >> flush_dcache_range(addr, addr + size); >> >> addr = (ulong)priv->rxbuffers; >> addr &= ~(ARCH_DMA_MINALIGN - 1); >> size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN); >> flush_dcache_range(addr, addr + size); >> barrier(); >> >> But since we actually want the uncached data invalidation seems logical. I >> have to admit though, I don't have much experience with caches. This patch >> completely fixed my problem... Maybe somebody with a bit more expertise can >> add their opinion? > > It should be 'invalidate' primitive when it comes to the RX path. For > TX path, it should be 'flush'.
+1 yes. Please retest with invalidate. Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
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