Hi Bin,
On Fri, 2018-12-07 at 06:14 -0800, Bin Meng wrote:
> This adds U-Boot syscon driver for SiFive's Core Local Interruptor
> (CLINT). The CLINT block holds memory-mapped control and status
> registers associated with software and timer interrupts.
>
> This driver implements the riscv_get_time() API as required by
> the generic RISC-V timer driver, as well as some other APIs that
> are needed for handling IPI.
>
> Signed-off-by: Bin Meng <bmeng...@gmail.com>
>
> ---
>
> Changes in v2:
> - rename the driver name to sifive_clint
> - save the clint base address to arch specific global data to support
> pre-relocation stage
> - remove the probe routine
> - add riscv_clear_ipi() API
>
> arch/riscv/Kconfig | 9 +++++
> arch/riscv/include/asm/global_data.h | 3 ++
> arch/riscv/include/asm/syscon.h | 19 ++++++++++
> arch/riscv/lib/Makefile | 1 +
> arch/riscv/lib/sifive_clint.c | 68
> ++++++++++++++++++++++++++++++++++++
> 5 files changed, 100 insertions(+)
> create mode 100644 arch/riscv/include/asm/syscon.h
> create mode 100644 arch/riscv/lib/sifive_clint.c
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 55c60e4..f513f52 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -95,4 +95,13 @@ config 32BIT
> config 64BIT
> bool
>
> +config SIFIVE_CLINT
> + bool
> + depends on RISCV_MMODE
> + select REGMAP
> + select SYSCON
> + help
> + The SiFive CLINT block holds memory-mapped control and status
> registers
> + associated with software and timer interrupts.
> +
> endmenu
> diff --git a/arch/riscv/include/asm/global_data.h
> b/arch/riscv/include/asm/global_data.h
> index 4d5d623..46fcfab 100644
> --- a/arch/riscv/include/asm/global_data.h
> +++ b/arch/riscv/include/asm/global_data.h
> @@ -12,6 +12,9 @@
>
> /* Architecture-specific global data */
> struct arch_global_data {
> +#ifdef CONFIG_SIFIVE_CLINT
> + void __iomem *clint; /* clint base address */
> +#endif
> };
>
> #include <asm-generic/global_data.h>
> diff --git a/arch/riscv/include/asm/syscon.h
> b/arch/riscv/include/asm/syscon.h
> new file mode 100644
> index 0000000..d311ee6
> --- /dev/null
> +++ b/arch/riscv/include/asm/syscon.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
> + */
> +
> +#ifndef _ASM_SYSCON_H
> +#define _ASM_SYSCON_H
> +
> +/*
> + * System controllers in a RISC-V system
> + *
> + * So far only SiFive's Core Local Interruptor (CLINT) is defined.
> + */
> +enum {
> + RISCV_NONE,
> + RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
> +};
> +
> +#endif /* _ASM_SYSCON_H */
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index b58db89..b13c876 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -9,6 +9,7 @@
> obj-$(CONFIG_CMD_BOOTM) += bootm.o
> obj-$(CONFIG_CMD_GO) += boot.o
> obj-y += cache.o
> +obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
> obj-y += interrupts.o
> obj-y += reset.o
> obj-y += setjmp.o
> diff --git a/arch/riscv/lib/sifive_clint.c
> b/arch/riscv/lib/sifive_clint.c
> new file mode 100644
> index 0000000..2d4bfac
> --- /dev/null
> +++ b/arch/riscv/lib/sifive_clint.c
> @@ -0,0 +1,68 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng...@gmail.com>
> + *
> + * U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
> + * The CLINT block holds memory-mapped control and status registers
> + * associated with software and timer interrupts.
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <regmap.h>
> +#include <syscon.h>
> +#include <asm/io.h>
> +#include <asm/syscon.h>
> +
> +/* MSIP registers */
> +#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
> +/* mtime compare register */
> +#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 +
> (hart) * 8)
> +/* mtime register */
> +#define MTIME_REG(base) ((ulong)(base) +
> 0xbff8)
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +u64 riscv_get_time(void)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);
This should work, but it is probably better to add error handling here
to detect if syscon_get_first_range has returned an error. The error
could then be propagated in the function return value. Same thing in
the functions below.
Thanks,
Lukas
> +
> + return readq((void __iomem *)MTIME_REG(gd->arch.clint));
> +}
> +
> +void riscv_set_timecmp(int hart, u64 cmp)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);
> +
> + writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint,
> hart));
> +}
> +
> +void riscv_send_ipi(int hart)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);
> +
> + writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +}
> +
> +void riscv_clear_ipi(int hart)
> +{
> + if (!gd->arch.clint)
> + gd->arch.clint =
> syscon_get_first_range(RISCV_SYSCON_CLINT);
> +
> + writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
> +}
> +
> +static const struct udevice_id sifive_clint_ids[] = {
> + { .compatible = "riscv,clint0", .data = RISCV_SYSCON_CLINT },
> + { }
> +};
> +
> +U_BOOT_DRIVER(sifive_clint) = {
> + .name = "sifive_clint",
> + .id = UCLASS_SYSCON,
> + .of_match = sifive_clint_ids,
> + .flags = DM_FLAG_PRE_RELOC,
> +};
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