Am 05.12.18 um 18:10 schrieb Gregory CLEMENT:
> Adding the support for 2 boards sharing common code for Ocelot chip:
> PCB120 and PCB123
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
> ---
> MAINTAINERS | 5 +
> arch/mips/dts/mscc,ocelot.dtsi | 152 +++++++++++++++++++++++++++
> arch/mips/dts/mscc,ocelot_pcb.dtsi | 42 ++++++++
> arch/mips/dts/ocelot_pcb120.dts | 12 +++
> arch/mips/dts/ocelot_pcb123.dts | 12 +++
> arch/mips/mach-mscc/Kconfig | 2 +
> board/mscc/ocelot/Kconfig | 14 +++
> board/mscc/ocelot/Makefile | 4 +
> board/mscc/ocelot/ocelot.c | 58 ++++++++++
> configs/mscc_ocelot_defconfig | 73 +++++++++++++
> configs/mscc_ocelot_pcb120_defconfig | 66 ++++++++++++
> include/configs/vcoreiii.h | 82 +++++++++++++++
> 12 files changed, 522 insertions(+)
> create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
> create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
> create mode 100644 arch/mips/dts/ocelot_pcb120.dts
> create mode 100644 arch/mips/dts/ocelot_pcb123.dts
> create mode 100644 board/mscc/ocelot/Kconfig
> create mode 100644 board/mscc/ocelot/Makefile
> create mode 100644 board/mscc/ocelot/ocelot.c
> create mode 100644 configs/mscc_ocelot_defconfig
> create mode 100644 configs/mscc_ocelot_pcb120_defconfig
> create mode 100644 include/configs/vcoreiii.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 53a3c5bec6..c906ca006b 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -490,6 +490,11 @@ M: Lars Povlsen <lars.povl...@microchip.com>
> M: Horatiu Vultur <horatiu.vul...@microchip.com>
> S: Maintained
> F: arch/mips/mach-mscc/
> +F: arch/mips/dts/mscc*
> +F: arch/mips/dts/ocelot*
> +F: board/mscc/
> +F: configs/mscc*
> +F: include/configs/vcoreiii.h
>
> MMC
> M: Jaehoon Chung <jh80.ch...@samsung.com>
> diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
> new file mode 100644
> index 0000000000..87b4736285
> --- /dev/null
> +++ b/arch/mips/dts/mscc,ocelot.dtsi
> @@ -0,0 +1,152 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "mscc,ocelot";
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu@0 {
> + compatible = "mips,mips24KEc";
> + device_type = "cpu";
> + clocks = <&cpu_clk>;
> + reg = <0>;
> + };
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + cpuintc: interrupt-controller@0 {
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + compatible = "mti,cpu-interrupt-controller";
> + };
> +
> + cpu_clk: cpu-clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <500000000>;
> + };
> +
> + ahb_clk: ahb-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <250000000>;
> + };
> +
> + ahb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x70000000 0x2000000>;
> +
> + interrupt-parent = <&intc>;
> +
> + cpu_ctrl: syscon@0 {
> + compatible = "mscc,ocelot-cpu-syscon", "syscon";
> + reg = <0x0 0x2c>;
> + };
> +
> + intc: interrupt-controller@70 {
> + compatible = "mscc,ocelot-icpu-intr";
> + reg = <0x70 0x70>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupt-parent = <&cpuintc>;
> + interrupts = <2>;
> + };
> +
> + uart0: serial@100000 {
> + pinctrl-0 = <&uart_pins>;
> + pinctrl-names = "default";
> + compatible = "ns16550a";
> + reg = <0x100000 0x20>;
> + interrupts = <6>;
> + clocks = <&ahb_clk>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@100800 {
> + pinctrl-0 = <&uart2_pins>;
> + pinctrl-names = "default";
> + compatible = "ns16550a";
> + reg = <0x100800 0x20>;
> + interrupts = <7>;
> + clocks = <&ahb_clk>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> +
> + status = "disabled";
> + };
> +
> + spi0: spi-master@101000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-ssi";
> + reg = <0x101000 0x40>;
> + num-chipselect = <4>;
> + bus-num = <0>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + spi-max-frequency = <18000000>; /* input clock */
> + clocks = <&ahb_clk>;
> +
> + status = "disabled";
> + };
> +
> + reset@1070008 {
> + compatible = "mscc,ocelot-chip-reset";
> + reg = <0x1070008 0x4>;
> + };
> +
> + gpio: pinctrl@1070034 {
> + compatible = "mscc,ocelot-pinctrl";
> + reg = <0x1070034 0x68>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = <&gpio 0 0 22>;
> +
> + uart_pins: uart-pins {
> + pins = "GPIO_6", "GPIO_7";
> + function = "uart";
> + };
> +
> + uart2_pins: uart2-pins {
> + pins = "GPIO_12", "GPIO_13";
> + function = "uart2";
> + };
> +
> + spi_cs1_pin: spi-cs1-pin {
> + pins = "GPIO_8";
> + function = "si";
> + };
> +
> + spi_cs2_pin: spi-cs2-pin {
> + pins = "GPIO_9";
> + function = "si";
> + };
> +
> + spi_cs3_pin: spi-cs3-pin {
> + pins = "GPIO_16";
> + function = "si";
> + };
> +
> + spi_cs4_pin: spi-cs4-pin {
> + pins = "GPIO_17";
> + function = "si";
> + };
> + };
> + };
> +};
> diff --git a/arch/mips/dts/mscc,ocelot_pcb.dtsi
> b/arch/mips/dts/mscc,ocelot_pcb.dtsi
> new file mode 100644
> index 0000000000..90725d3b94
> --- /dev/null
> +++ b/arch/mips/dts/mscc,ocelot_pcb.dtsi
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +/dts-v1/;
> +#include "mscc,ocelot.dtsi"
> +
> +/ {
> + compatible = "mscc,ocelot";
> +
> + aliases {
> + spi0 = &spi0;
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&spi0 {
> + status = "okay";
> + pinctrl-0 = <&spi_cs1_pin>;
> + pinctrl-names = "default";
> +
> + spi-flash@0 {
> + compatible = "spi-flash";
> + spi-max-frequency = <18000000>; /* input clock */
> + reg = <0>; /* CS0 */
> + };
> +
> + spi-nand@1 {
> + compatible = "spi-nand";
> + spi-max-frequency = <18000000>; /* input clock */
> + reg = <1>; /* CS1 */
> + };
> +};
> diff --git a/arch/mips/dts/ocelot_pcb120.dts b/arch/mips/dts/ocelot_pcb120.dts
> new file mode 100644
> index 0000000000..47d305a614
> --- /dev/null
> +++ b/arch/mips/dts/ocelot_pcb120.dts
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +/dts-v1/;
> +#include "mscc,ocelot_pcb.dtsi"
> +
> +/ {
> + model = "Ocelot PCB120 Reference Board";
> + compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
> +};
> diff --git a/arch/mips/dts/ocelot_pcb123.dts b/arch/mips/dts/ocelot_pcb123.dts
> new file mode 100644
> index 0000000000..17d8d326ce
> --- /dev/null
> +++ b/arch/mips/dts/ocelot_pcb123.dts
> @@ -0,0 +1,12 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +/dts-v1/;
> +#include "mscc,ocelot_pcb.dtsi"
> +
> +/ {
> + model = "Ocelot PCB123 Reference Board";
> + compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
> +};
> diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
> index a8cace0e79..fc806fc1f3 100644
> --- a/arch/mips/mach-mscc/Kconfig
> +++ b/arch/mips/mach-mscc/Kconfig
> @@ -79,4 +79,6 @@ config DDRTYPE_MT47H128M8HQ
>
> endchoice
>
> +source "board/mscc/ocelot/Kconfig"
> +
> endmenu
> diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
> new file mode 100644
> index 0000000000..9ddc0880b1
> --- /dev/null
> +++ b/board/mscc/ocelot/Kconfig
> @@ -0,0 +1,14 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +config SYS_VENDOR
> + default "mscc"
> +
> +if SOC_OCELOT
> +
> +config SYS_BOARD
> + default "ocelot"
> +
> +config SYS_CONFIG_NAME
> + default "ocelot"
> +
> +endif
> diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile
> new file mode 100644
> index 0000000000..9f28c81268
> --- /dev/null
> +++ b/board/mscc/ocelot/Makefile
> @@ -0,0 +1,4 @@
> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +
> +obj-$(CONFIG_SOC_OCELOT) := ocelot.o
> +
> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
> new file mode 100644
> index 0000000000..d521a61957
> --- /dev/null
> +++ b/board/mscc/ocelot/ocelot.c
> @@ -0,0 +1,58 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <asm/addrspace.h>
> +#include <asm/types.h>
> +#include <environment.h>
> +#include <spi.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#define MSCC_GPIO_ALT0 0x54
> +#define MSCC_GPIO_ALT1 0x58
> +
> +void external_cs_manage(struct udevice *dev, bool enable)
> +{
> + u32 cs = spi_chip_select(dev);
> + /* IF_SI0_OWNER, select the owner of the SI interface
> + * Encoding: 0: SI Slave
> + * 1: SI Boot Master
> + * 2: SI Master Controller
> + */
> + if (!enable) {
> + writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
> + ICPU_SW_MODE_SW_SPI_CS(BIT(cs)), BASE_CFG +
> ICPU_SW_MODE);
> + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
> + ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
> + ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
> + } else {
> + writel(0, BASE_CFG + ICPU_SW_MODE);
> + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
> + ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
> + ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
> + }
> +}
> +
> +void board_debug_uart_init(void)
> +{
> + /* too early for the pinctrl driver, so configure the UART pins here */
> + setbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT0, BIT(6) | BIT(7));
> + clrbits_le32(BASE_DEVCPU_GCB + MSCC_GPIO_ALT1, BIT(6) | BIT(7));
> +}
> +
> +int board_early_init_r(void)
> +{
> + /* Prepare SPI controller to be used in master mode */
> + writel(0, BASE_CFG + ICPU_SW_MODE);
> + clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
> + ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
> + ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
> +
> + /* Address of boot parameters */
> + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
> + return 0;
> +}
> diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig
> new file mode 100644
> index 0000000000..6de047a8de
> --- /dev/null
> +++ b/configs/mscc_ocelot_defconfig
> @@ -0,0 +1,73 @@
> +CONFIG_MIPS=y
> +CONFIG_SYS_TEXT_BASE=0x40000000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_DEBUG_UART_BOARD_INIT=y
> +CONFIG_DEBUG_UART_BASE=0x70100000
> +CONFIG_DEBUG_UART_CLOCK=250000000
> +CONFIG_ARCH_MSCC=y
> +CONFIG_TARGET_OCELOT_PCB123=y
> +CONFIG_SYS_LITTLE_ENDIAN=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="console=ttyS0,115200"
> +CONFIG_LOGLEVEL=7
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_SYS_PROMPT="pcb123 # "
> +# CONFIG_CMD_BDI is not set
> +# CONFIG_CMD_CONSOLE is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_MD5SUM=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_MTD=y
> +CONFIG_CMD_UBI=y
> +# CONFIG_CMD_UBIFS is not set
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_DHCP=y
> +# CONFIG_NET_TFTP_VARS is not set
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
you should recheck all MTD related options due to some recent changes in
mainline
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_OF_EMBED=y
> +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123"
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MTD_PARTITIONS=y
> +CONFIG_MTD=y
> +CONFIG_MTD_NAND_CORE=y
> +CONFIG_MTD_SPI_NAND=y
> +CONFIG_MTD_UBI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCONF=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_DEBUG_UART_ANNOUNCE=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_SPI_MEM=y
> +CONFIG_DESIGNWARE_SPI=y
> +CONFIG_LZMA=y
> diff --git a/configs/mscc_ocelot_pcb120_defconfig
> b/configs/mscc_ocelot_pcb120_defconfig
> new file mode 100644
> index 0000000000..3ba7ea91f9
> --- /dev/null
> +++ b/configs/mscc_ocelot_pcb120_defconfig
> @@ -0,0 +1,66 @@
> +CONFIG_MIPS=y
> +CONFIG_SYS_TEXT_BASE=0x40000000
> +CONFIG_SYS_MALLOC_F_LEN=0x2000
> +CONFIG_ARCH_MSCC=y
> +CONFIG_SYS_LITTLE_ENDIAN=y
> +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120"
> +CONFIG_FIT=y
> +CONFIG_BOOTDELAY=3
> +CONFIG_USE_BOOTARGS=y
> +CONFIG_BOOTARGS="console=ttyS0,115200"
> +CONFIG_LOGLEVEL=7
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_SYS_PROMPT="pcb120 # "
> +# CONFIG_CMD_BDI is not set
> +# CONFIG_CMD_CONSOLE is not set
> +# CONFIG_CMD_ELF is not set
> +# CONFIG_CMD_EXPORTENV is not set
> +# CONFIG_CMD_IMPORTENV is not set
> +# CONFIG_CMD_CRC32 is not set
> +CONFIG_CMD_MD5SUM=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_MEMTEST=y
> +# CONFIG_CMD_FLASH is not set
> +CONFIG_CMD_GPIO=y
> +CONFIG_CMD_MTD=y
> +CONFIG_CMD_UBI=y
> +# CONFIG_CMD_UBIFS is not set
> +CONFIG_CMD_SF=y
> +CONFIG_CMD_SPI=y
> +CONFIG_CMD_DHCP=y
> +# CONFIG_NET_TFTP_VARS is not set
> +# CONFIG_CMD_NFS is not set
> +CONFIG_CMD_PING=y
> +CONFIG_CMD_MTDPARTS=y
> +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash"
> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)"
> +# CONFIG_ISO_PARTITION is not set
> +CONFIG_OF_EMBED=y
> +CONFIG_ENV_IS_IN_SPI_FLASH=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_CLK=y
> +CONFIG_DM_GPIO=y
> +CONFIG_MTD_PARTITIONS=y
> +CONFIG_MTD=y
> +CONFIG_MTD_NAND_CORE=y
> +CONFIG_MTD_SPI_NAND=y
> +CONFIG_MTD_UBI=y
> +CONFIG_DM_SPI_FLASH=y
> +CONFIG_SPI=y
> +CONFIG_SPI_FLASH=y
> +CONFIG_SPI_FLASH_BAR=y
> +CONFIG_SPI_FLASH_GIGADEVICE=y
> +CONFIG_SPI_FLASH_MACRONIX=y
> +CONFIG_SPI_FLASH_SPANSION=y
> +CONFIG_SPI_FLASH_WINBOND=y
> +CONFIG_SPI_FLASH_MTD=y
> +CONFIG_DM_ETH=y
> +CONFIG_PINCTRL=y
> +CONFIG_PINCONF=y
> +CONFIG_DM_SERIAL=y
> +CONFIG_SYS_NS16550=y
> +CONFIG_SPI=y
> +CONFIG_DM_SPI=y
> +CONFIG_SPI_MEM=y
> +CONFIG_DESIGNWARE_SPI=y
> +CONFIG_LZMA=y
> diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h
> new file mode 100644
> index 0000000000..df89cdaebf
> --- /dev/null
> +++ b/include/configs/vcoreiii.h
> @@ -0,0 +1,82 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
this line should begin with //
> +/*
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#ifndef __VCOREIII_H
> +#define __VCOREIII_H
> +
> +#include <linux/sizes.h>
> +
> +/* Onboard devices */
> +
> +#define CONFIG_SYS_MALLOC_LEN 0x100000
> +#define CONFIG_SYS_LOAD_ADDR 0x00100000
> +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
> +
> +#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS
> core */
> +#ifdef CONFIG_SOC_LUTON
> +#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333
> +#else
> +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2)
> +#endif
> +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ
> +
> +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
> +#define CONFIG_ENV_OFFSET (1024 * 1024)
> +#define CONFIG_ENV_SIZE (256 * 1024)
> +#define CONFIG_ENV_SECT_SIZE (256 * 1024)
> +
> +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
> +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
> +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET +
> CONFIG_ENV_SECT_SIZE)
> +
> +#define CONFIG_ENV_SPI_MAX_HZ 0 /* This force to read from DT
> */
> +#define CONFIG_ENV_SPI_MODE 0 /* This force to read from DT */
> +#endif
> +
> +#define CONFIG_SYS_SDRAM_BASE 0x80000000
> +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) ||
> defined(CONFIG_DDRTYPE_MT47H128M8HQ)
> +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M)
> +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) ||
> defined(CONFIG_DDRTYPE_MT41K128M16JT)
> +#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M)
> +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) ||
> defined(CONFIG_DDRTYPE_MT41K256M16)
> +#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M)
> +#else
> +#error Unknown DDR size - please add!
> +#endif
> +
> +#define CONFIG_CONS_INDEX 1
> +
> +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
> +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE +
> CONFIG_SYS_SDRAM_SIZE - SZ_1M)
> +
> +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
> +
> +#define CONFIG_BOARD_EARLY_INIT_R
> +#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)
> +#define VCOREIII_DEFAULT_MTD_ENV \
> + "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" \
> + "mtdids="CONFIG_MTDIDS_DEFAULT"\0"
> +#else
> +#define VCOREIII_DEFAULT_MTD_ENV /* Go away */
> +#endif
> +
> +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip
> size */
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> + VCOREIII_DEFAULT_MTD_ENV \
> + "loadaddr=0x81000000\0" \
> + "spi_image_off=0x00100000\0" \
> + "console=ttyS0,115200\0" \
> + "setup=setenv bootargs console=${console} ${mtdparts}" \
> + "${bootargs_extra}\0" \
> + "spiboot=run setup; sf probe; sf read ${loadaddr}" \
> + "${spi_image_off} 0x600000; bootm ${loadaddr}\0" \
> + "ubootfile=u-boot.bin\0" \
> + "update=sf probe;mtdparts;dhcp ${loadaddr} ${ubootfile};" \
> + "sf erase UBoot 0x100000;" \
> + "sf write ${loadaddr} UBoot ${filesize}\0" \
> + "bootcmd=run spiboot\0" \
> + ""
> +#endif /* __VCOREIII_H */
>
--
- Daniel
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