With logical AND - we exit the memory setup procedure on any interrupt -
also on errors.
Signed-off-by: Lukasz Majewski <lu...@denx.de>
---
arch/arm/mach-imx/ddrmc-vf610.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index 3d7da1c25e..ea6a49e0fa 100644
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -231,6 +231,6 @@ void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const
*timings,
/* all inits done, start the DDR controller */
writel(DDRMC_CR00_DRAM_CLASS_DDR3 | DDRMC_CR00_START, &ddrmr->cr[0]);
- while (!(readl(&ddrmr->cr[80]) && 0x100))
+ while (!(readl(&ddrmr->cr[80]) & 0x100))
udelay(10);
}
--
2.11.0
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