On 11/28/2018 05:17 PM, Chee, Tien Fong wrote: > On Wed, 2018-11-28 at 16:10 +0100, Marek Vasut wrote: >> On 11/28/2018 03:49 PM, Chee, Tien Fong wrote: >>> >>> On Tue, 2018-11-27 at 13:07 +0100, Marek Vasut wrote: >>>> >>>> On 11/27/2018 09:45 AM, Chee, Tien Fong wrote: >>>>> >>>>> >>>>> On Mon, 2018-11-26 at 12:15 +0100, Marek Vasut wrote: >>>>>> >>>>>> >>>>>> On 11/26/2018 10:44 AM, Chee, Tien Fong wrote: >>>>>>> >>>>>>> >>>>>>> >>>>>>> On Fri, 2018-11-23 at 13:23 +0100, Marek Vasut wrote: >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> On 11/23/2018 10:19 AM, Chee, Tien Fong wrote: >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> On Wed, 2018-11-21 at 15:11 +0100, Marek Vasut wrote: >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> On 11/21/2018 11:41 AM, tien.fong.c...@intel.com >>>>>>>>>> wrote: >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> >>>>>>>>>>> From: Tien Fong Chee <tien.fong.c...@intel.com> >>>>>>>>>>> >>>>>>>>>>> This patch adds description on properties about >>>>>>>>>>> file >>>>>>>>>>> name >>>>>>>>>>> used >>>>>>>>>>> for >>>>>>>>>>> both >>>>>>>>>>> peripheral bitstream and core bitstream. >>>>>>>>>>> >>>>>>>>>>> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel >>>>>>>>>>> .com >>>>>>>>>>>> >>>>>>>>>>>> >>>>>>>>>>> --- >>>>>>>>>>> .../fpga/altera-socfpga-a10-fpga- >>>>>>>>>>> mgr.txt | 6 >>>>>>>>>>> ++++++ >>>>>>>>>>> 1 files changed, 6 insertions(+), 0 deletions(-) >>>>>>>>>>> >>>>>>>>>>> diff --git a/doc/device-tree-bindings/fpga/altera- >>>>>>>>>>> socfpga- >>>>>>>>>>> a10- >>>>>>>>>>> fpga- >>>>>>>>>>> mgr.txt b/doc/device-tree-bindings/fpga/altera- >>>>>>>>>>> socfpga- >>>>>>>>>>> a10- >>>>>>>>>>> fpga- >>>>>>>>>>> mgr.txt >>>>>>>>>>> index 2fd8e7a..010322a 100644 >>>>>>>>>>> --- a/doc/device-tree-bindings/fpga/altera-socfpga- >>>>>>>>>>> a10- >>>>>>>>>>> fpga- >>>>>>>>>>> mgr.txt >>>>>>>>>>> +++ b/doc/device-tree-bindings/fpga/altera-socfpga- >>>>>>>>>>> a10- >>>>>>>>>>> fpga- >>>>>>>>>>> mgr.txt >>>>>>>>>>> @@ -7,6 +7,10 @@ Required properties: >>>>>>>>>>> - The second index is for writing >>>>>>>>>>> FPGA >>>>>>>>>>> configuration data. >>>>>>>>>>> - resets : Phandle and reset specifier for the >>>>>>>>>>> device's >>>>>>>>>>> reset. >>>>>>>>>>> - clocks : Clocks used by the device. >>>>>>>>>>> +- altr,bitstream_periph : File name for FPGA >>>>>>>>>>> peripheral >>>>>>>>>>> raw >>>>>>>>>>> binary >>>>>>>>>>> which is used >>>>>>>>>>> + to initialize FPGA IOs, >>>>>>>>>>> PLL, >>>>>>>>>>> IO48 >>>>>>>>>>> and >>>>>>>>>>> DDR. >>>>>>>>>>> +- altr,bitstream_core : File name for core raw >>>>>>>>>>> binary >>>>>>>>>>> which >>>>>>>>>>> contains FPGA design >>>>>>>>>>> + which is used to program >>>>>>>>>>> FPGA >>>>>>>>>>> CRAM >>>>>>>>>>> and >>>>>>>>>>> ERAM. >>>>>>>>>> bitstream- instead of bitstream_ >>>>>>>>> Noted. >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> btw can we get something that works with full >>>>>>>>>> bitstream >>>>>>>>>> too ? >>>>>>>>> This patchset actually support the full bitstream too, >>>>>>>>> unfortunately it >>>>>>>>> is blocked by hardware MPFE issue. The patchset for the >>>>>>>>> MPFE >>>>>>>>> workaround >>>>>>>>> would come after this patchset. I would advice to use >>>>>>>>> the >>>>>>>>> early >>>>>>>>> IO >>>>>>>>> release method for the sake of performance. >>>>>>>>> >>>>>>>>> For details of issue, you can read the from the >>>>>>>>> link https: >>>>>>>>> //gi >>>>>>>>> thub >>>>>>>>> .com >>>>>>>>> /altera-opensource/u-boot- >>>>>>>>> socfpga/commits/socfpga_v2014.10_arria10_brin >>>>>>>>> gup >>>>>>>>> FogBugz #410989-6: Masking hardware sequenced warm >>>>>>>>> reset >>>>>>>>> for >>>>>>>>> logic >>>>>>>>> in… … >>>>>>>> Does that work on ES2 ? I don't think so ... >>>>>>> Why you think it doesn't work, using early IO or full rbf? >>>>>>> The >>>>>>> bitstream limitation? What you see from the print out? >>>>>> ES2 can only use full RBF, I don't think this is handled in >>>>>> this >>>>>> patchset at all. >>>>> i did testing the full rbf loading, but in the end i removed >>>>> that >>>>> portion of codes because it stuck in DDR calibration due to >>>>> MPFE HW >>>>> issue. So, i would put back that portion of codes after MPFE HW >>>>> workaround. My plan is to let early IO release up 1st. >>>> Can you describe that workaround ? The code worked on the A10ES2 >>>> kit >>>> I >>>> have back around v2018.09, so what's the problem ? > There is a corruption to MPFE NoC(which function like ethernet QOS, but > its main function for priotizing and controlling traffic to access DDR > from MPU and FPGA) due to high fequency transient clock out from HPS > EMIF IOPLL at VCO startup. The corruption happens intermittent on some > boards. The workaround is to trigger warm reset to recover MPFE NoC > from corruption after programing the periph rbf or full rbf. Once U- > Boot reentrance after warm reset, only core rbf is allowed to > configured FPGA.
And this is present in ES1 or ES2 ? Or is it also in PS ? I wonder whether we want to scrap the ES support afterall. -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
