On 11/14/2018 12:40 AM, Marek Vasut wrote: > Switch the driver to using clk_get_rate()/clk_set_rate() instead of > caching the mclk frequency in it's private data. This is required on > the SDHI variant of the controller, where the upstream mclk need to > be adjusted when using UHS modes. > > Platforms which do not support clock framework or do not support it > in eg. SPL default to 100 MHz clock. > > Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com> > Cc: Masahiro Yamada <yamada.masah...@socionext.com>
Yamada-san, can you please check 1/6..3/6 ? Thanks ! -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
