From: Tien Fong Chee <tien.fong.c...@intel.com>
These series of patches enable peripheral bitstream being programmed into FPGA
to get the DDR up running. This's also called early IO release, because the
peripheral bitstream is only initializing FPGA IOs, PLL, IO48 and DDR.
Once DDR is up running, core bitstream from FIT image which contains user FPGA
design would be loaded into DDR location, where it's defined as 0x1000 by
default in fit_spl_fpga.its. fpga load would be called to program core bitstream
into FPGA and entering user mode.
Lastly, U-Boot from FIT image would be loaded to DDR, and up running from there.
For the whole mechanism to work, the SDMMC flash layout would be designed as
shown in below:
RAW partition:
1. spl_w_dtb-mkpimage.bin
mkpimage -hv 1 -o spl/spl_w_dtb-mkpimage.bin spl/u-boot-spl-dtb.bin
spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin spl/u-boot-spl-dtb.bin
FAT partition:
1. u-boot.itb(default build)
- uboot
- fdt
- fpga
2. ghrd_10as066n2.periph.rbf.mkimage
mkimage -A arm -T firmware -C none -O u-boot -a 0 -e 0 -n \"RBF\" -d
ghrd_10as066n2.periph.rbf ghrd_10as066n2.periph.rbf.mkimage
This series is working on top of u-boot.git -
http://git.denx.de/u-boot.git .
Tien Fong Chee (9):
ARM: socfpga: Description on FPGA bitstream type and file name for
Arria 10
ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
spl : socfpga: Implement fpga bitstream loading with socfpga loadfs
ARM: socfpga: Bundle U-Boot fitImage into SFP on Arria10
ARM: socfpga: Add SPL fitImage config match
ARM: socfpga: Set default DTB address on A10
ARM: socfpga: Use custom header target buffer in SPL
ARM: socfpga: Add default fitImage for Arria10 SoCDK
ARM: socfpga: Synchronize the configuration for A10 SoCDK
Makefile | 9 +-
arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 +
arch/arm/mach-socfpga/board.c | 8 +
.../include/mach/fpga_manager_arria10.h | 30 ++-
arch/arm/mach-socfpga/spl_a10.c | 70 ++++-
board/altera/arria10-socdk/fit_spl_fpga.its | 54 +++
common/spl/spl_mmc.c | 2 +-
configs/socfpga_arria10_defconfig | 51 +++-
.../fpga/altera-socfpga-a10-fpga-mgr.txt | 6 +
drivers/fpga/Kconfig | 9 +
drivers/fpga/socfpga_arria10.c | 417 +++++++++++++++++++-
include/configs/socfpga_common.h | 4 +
include/mmc.h | 1 +
13 files changed, 657 insertions(+), 22 deletions(-)
create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its
--
1.7.7.4
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