On Tue, Nov 20, 2018 at 7:08 PM Bin Meng <bmeng...@gmail.com> wrote: > > Hi Anup, > > On Tue, Nov 20, 2018 at 7:29 PM Anup Patel <a...@brainfault.org> wrote: > > > > This patch adds kconfig option RISCV_SMODE to run u-boot in > > S-mode. When this opition is enabled we use s<xyz> CSRs instead > > of m<xyz> CSRs. > > > > It is important to note that there is no equivalent S-mode CSR > > for misa and mhartid CSRs so we expect M-mode runtime firmware > > (BBL or equivalent) to emulate misa and mhartid CSR read. > > > > Eventually, we will have patches to avoid accessing misa and > > mhartid from S-mode. > > > > What patches?
What I meant was in-future we will have more patches to avoid accessing misa and mhartid from S-mode. I will re-phrase it. > > > Signed-off-by: Anup Patel <a...@brainfault.org> > > --- > > arch/riscv/Kconfig | 6 ++++++ > > arch/riscv/cpu/start.S | 33 +++++++++++++++++++++++++++++++++ > > 2 files changed, 39 insertions(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 3e0af55e71..88bc0d2a43 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -55,6 +55,12 @@ config RISCV_ISA_C > > config RISCV_ISA_A > > def_bool y > > > > +config RISCV_SMODE > > + bool "Run in S-Mode" > > + default n > > nits: 'default n' is not needed Sure, I will drop it. > > > + help > > + Enable this option to build an U-Boot for RISC-V S-Mode > > + > > config 32BIT > > bool > > > > [snip] > > Other than that, > > Reviewed-by: Bin Meng <bmeng...@gmail.com> > Tested-by: Bin Meng <bmeng...@gmail.com> Thanks, Anup _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
