Hi Benjamin
On 11/14/18 10:01 AM, Benjamin Gaignard wrote:
> From: Benjamin Gaignard <benjamin.gaign...@linaro.org>
>
> Add hardware spinlock in the list of the clocks.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaign...@linaro.org>
> ---
> drivers/clk/clk_stm32mp1.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
> index 6a8c7b754f..b7c5d34fe0 100644
> --- a/drivers/clk/clk_stm32mp1.c
> +++ b/drivers/clk/clk_stm32mp1.c
> @@ -104,6 +104,7 @@
> #define RCC_MP_APB2ENSETR 0XA08
> #define RCC_MP_APB3ENSETR 0xA10
> #define RCC_MP_AHB2ENSETR 0xA18
> +#define RCC_MP_AHB3ENSETR 0xA20
> #define RCC_MP_AHB4ENSETR 0xA28
>
> /* used for most of SELR register */
> @@ -534,6 +535,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[]
> = {
> STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 8, USBO_K, _USBO_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL),
>
> + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL),
> +
> STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
> STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 2, GPIOC, _UNKNOWN_SEL),
>
Reviewed-by: Patrice Chotard <patrice.chot...@st.com>
Thanks
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