On Fri, Oct 12, 2018 at 12:46 PM Ryder Lee <ryder....@mediatek.com> wrote: > > From: Guochun Mao <guochun....@mediatek.com> > > This patch adds MT7629 qspi driver for accessing SPI NOR flash. > > Cc: Jagan Teki <ja...@openedev.com> > Signed-off-by: Guochun Mao <guochun....@mediatek.com> > --- > change since v2: > - Drop flash commands in the driver. > --- > drivers/spi/Kconfig | 7 + > drivers/spi/Makefile | 1 + > drivers/spi/mtk_qspi.c | 359 > +++++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 367 insertions(+) > create mode 100644 drivers/spi/mtk_qspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 1df6876..f9cf4ba 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -124,6 +124,13 @@ config MT7621_SPI > the SPI NOR flash on platforms embedding this Ralink / MediaTek > SPI core, like MT7621/7628/7688. > > +config MTK_QSPI > + bool "Mediatek QSPI driver" > + help > + Enable the Mediatek QSPI driver. This driver can be > + used to access the SPI NOR flash on platforms embedding this > + Mediatek QSPI IP core. > + > config MVEBU_A3700_SPI > bool "Marvell Armada 3700 SPI driver" > select CLK_ARMADA_3720 > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 7242ea7..e5a78f5 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -33,6 +33,7 @@ obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o > obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o > obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o > obj-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o > +obj-$(CONFIG_MTK_QSPI) += mtk_qspi.o > obj-$(CONFIG_MT7621_SPI) += mt7621_spi.o > obj-$(CONFIG_MVEBU_A3700_SPI) += mvebu_a3700_spi.o > obj-$(CONFIG_MXC_SPI) += mxc_spi.o > diff --git a/drivers/spi/mtk_qspi.c b/drivers/spi/mtk_qspi.c > new file mode 100644 > index 0000000..b510733 > --- /dev/null > +++ b/drivers/spi/mtk_qspi.c > @@ -0,0 +1,359 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Copyright (c) 2018 MediaTek, Inc. > + * Author : guochun....@mediatek.com > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <malloc.h> > +#include <spi.h> > +#include <asm/io.h> > +#include <linux/iopoll.h> > +#include <linux/ioport.h> > + > +/* Register Offset */ > +struct mtk_qspi_regs { > + u32 cmd; > + u32 cnt; > + u32 rdsr; > + u32 rdata; > + u32 radr[3]; > + u32 wdata; > + u32 prgdata[6]; > + u32 shreg[10]; > + u32 cfg[2]; > + u32 shreg10; > + u32 mode_mon; > + u32 status[4]; > + u32 flash_time; > + u32 flash_cfg; > + u32 reserved_0[3]; > + u32 sf_time; > + u32 pp_dw_data; > + u32 reserved_1; > + u32 delsel_0[2]; > + u32 intrstus; > + u32 intren; > + u32 reserved_2; > + u32 cfg3; > + u32 reserved_3; > + u32 chksum; > + u32 aaicmd; > + u32 wrprot; > + u32 radr3; > + u32 dual; > + u32 delsel_1[3]; > +}; > + > +struct mtk_qspi_platdata { > + fdt_addr_t reg_base; > + fdt_addr_t mem_base; > +}; > + > +struct mtk_qspi_priv { > + struct mtk_qspi_regs *regs; > + unsigned long *mem_base; > + u8 op; > + u8 tx[3]; /* only record max 3 bytes paras, when it's address. */ > + u32 txlen; /* dout buffer length - op code length */ > + u8 *rx; > + u32 rxlen; > +}; > + > +#define MTK_QSPI_CMD_POLLINGREG_US 500000 > +#define MTK_QSPI_WRBUF_SIZE 256 > +#define MTK_QSPI_COMMAND_ENABLE 0x30 > + > +/* NOR flash controller commands */ > +#define MTK_QSPI_RD_TRIGGER BIT(0) > +#define MTK_QSPI_READSTATUS BIT(1) > +#define MTK_QSPI_PRG_CMD BIT(2) > +#define MTK_QSPI_WR_TRIGGER BIT(4) > +#define MTK_QSPI_WRITESTATUS BIT(5) > +#define MTK_QSPI_AUTOINC BIT(7) > + > +#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6 > +#define MTK_QSPI_MAX_SHIFT 0x8 > + > +#define MTK_QSPI_WR_BUF_ENABLE 0x1 > +#define MTK_QSPI_WR_BUF_DISABLE 0x0
All these bits look flash handling bit's , aren't ? > + > +static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd) > +{ > + u8 tmp; > + u8 val = cmd & ~MTK_QSPI_AUTOINC; > + > + writeb(cmd, &priv->regs->cmd); > + > + return readb_poll_timeout(&priv->regs->cmd, tmp, !(val & tmp), > + MTK_QSPI_CMD_POLLINGREG_US); > +} > + > +static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv) > +{ > + int len = 1 + priv->txlen + priv->rxlen; > + int i, ret, idx; > + > + if (len > MTK_QSPI_MAX_SHIFT) > + return -ERR_INVAL; > + > + writeb(len * 8, &priv->regs->cnt); > + > + /* start at PRGDATA5, go down to PRGDATA0 */ > + idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1; > + > + /* opcode */ > + writeb(priv->op, &priv->regs->prgdata[idx]); > + idx--; > + > + /* program TX data */ > + for (i = 0; i < priv->txlen; i++, idx--) > + writeb(priv->tx[i], &priv->regs->prgdata[idx]); > + > + /* clear out rest of TX registers */ > + while (idx >= 0) { > + writeb(0, &priv->regs->prgdata[idx]); > + idx--; > + } > + > + ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD); What does this execute do? does it intiate the controller register based flash command or so? Do you have Linux driver on the controller? _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot