From: Hou Zhiqiang <zhiqiang....@nxp.com>
The lx2160a have up to 6 PCIe controllers and have different
address and size of PCIe region.
Signed-off-by: Hou Zhiqiang <zhiqiang....@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 12 ++++++++++++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 2 ++
.../include/asm/arch-fsl-layerscape/immap_lsch3.h | 14 +++++++++++++-
3 files changed, 27 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index a35958a9ee..bfde3934aa 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -255,6 +255,18 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#endif
+#ifdef CONFIG_ARCH_LX2160A
+ { SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
+ SYS_PCIE5_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ { SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
+ SYS_PCIE6_PHYS_SIZE,
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE,
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index b4bd2c604a..678ffe5e7a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -44,6 +44,8 @@
#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000
+#define SYS_PCIE5_PHYS_SIZE 0x800000000
+#define SYS_PCIE6_PHYS_SIZE 0x800000000
#endif
#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 2ed6b99fad..0662745962 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -167,7 +167,19 @@
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
-#ifdef CONFIG_ARCH_LS1088A
+#ifdef CONFIG_ARCH_LX2160A
+#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
+#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
+#endif
+
+#ifdef CONFIG_ARCH_LX2160A
+#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
+#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
+#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
+#elif CONFIG_ARCH_LS1088A
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
--
2.17.1
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