This patch supports the Altera CycloneIII Nios dev board using
the example FPGA design at http://nioswiki.com/Linux.
Signed-off-by: Thomas Chou <tho...@wytron.com.tw>
---
MAINTAINERS | 1 +
MAKEALL | 1 +
Makefile | 2 +-
board/altera/nios2-generic/default_mmu.h | 371 ++++++++++++++++++++++++++++
include/configs/EP3C120.h | 394 ++++++++++++++++++++++++++++++
5 files changed, 768 insertions(+), 1 deletions(-)
create mode 100644 board/altera/nios2-generic/default_mmu.h
create mode 100644 include/configs/EP3C120.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 1f33146..30ac451 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -851,6 +851,7 @@ Scott McNutt <smcn...@psyent.com>
EP1S10 Nios-II
EP1S40 Nios-II
EP2C35 Nios-II
+ EP3C120 Nios-II
#########################################################################
# MicroBlaze Systems: #
diff --git a/MAKEALL b/MAKEALL
index 8ab3358..886d608 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -824,6 +824,7 @@ LIST_nios2=" \
PCI5441 \
PK1C20 \
EP2C35 \
+ EP3C120 \
"
#########################################################################
diff --git a/Makefile b/Makefile
index a27b002..5b3c589 100644
--- a/Makefile
+++ b/Makefile
@@ -3534,7 +3534,7 @@ PCI5441_config : unconfig
@$(MKCONFIG) PCI5441 nios2 nios2 pci5441 psyent
# nios2 generic boards
-NIOS2_GENERIC = EP2C35
+NIOS2_GENERIC = EP2C35 EP3C120
$(NIOS2_GENERIC:%=%_config) : unconfig
@$(MKCONFIG) $(@:_config=) nios2 nios2 nios2-generic altera
diff --git a/board/altera/nios2-generic/default_mmu.h
b/board/altera/nios2-generic/default_mmu.h
new file mode 100644
index 0000000..dc14dc2
--- /dev/null
+++ b/board/altera/nios2-generic/default_mmu.h
@@ -0,0 +1,371 @@
+#ifndef _ALTERA_LINUX_CPU_H_
+#define _ALTERA_LINUX_CPU_H_
+
+/* Note, this file was manually edited after generation
+ * since the multiple inclusion proctetion macro above collides with
+ * include/linux/cpu.h
+ */
+
+/*
+ * This file was automatically generated by the swinfo2header utility.
+ *
+ * Created from SOPC Builder system 'nios2_linux_3c120_125mhz_sys_sopc' in
+ * file 'default//nios2_linux_3c120_125mhz_sys_sopc.sopcinfo'.
+ */
+
+/*
+ * This file contains macros for module 'linux_cpu' and devices
+ * connected to the following masters:
+ * instruction_master
+ * tightly_coupled_instruction_master_0
+ * data_master
+ * tightly_coupled_data_master_0
+ *
+ * Do not #include this header file and another header file created for a
+ * different module or master group at the same time.
+ * Doing so may result in duplicate #defines.
+ * Instead, use the system header file which has #defines with unique names.
+ */
+
+/*
+ * Macros for module 'linux_cpu', class 'altera_nios2'.
+ * The macros have no prefix.
+ */
+#define CPU_IMPLEMENTATION "fast"
+#define ICACHE_LINE_SIZE 32
+#define ICACHE_LINE_SIZE_LOG2 5
+#define ICACHE_SIZE 32768
+#define DCACHE_LINE_SIZE 32
+#define DCACHE_LINE_SIZE_LOG2 5
+#define DCACHE_SIZE 32768
+#define INITDA_SUPPORTED
+#define FLUSHDA_SUPPORTED
+#define HAS_JMPI_INSTRUCTION
+#define MMU_PRESENT
+#define KERNEL_REGION_BASE 0xc0000000
+#define IO_REGION_BASE 0xe0000000
+#define KERNEL_MMU_REGION_BASE 0x80000000
+#define USER_REGION_BASE 0x0
+#define PROCESS_ID_NUM_BITS 8
+#define TLB_NUM_WAYS 16
+#define TLB_PTR_SZ 7
+#define TLB_NUM_ENTRIES 128
+#define FAST_TLB_MISS_EXCEPTION_ADDR 0xc7fff400
+#define EXCEPTION_ADDR 0xd0000020
+#define RESET_ADDR 0xc2800000
+#define BREAK_ADDR 0xc7fff820
+#define HAS_DEBUG_STUB
+#define HAS_DEBUG_CORE 1
+#define HAS_ILLEGAL_INSTRUCTION_EXCEPTION
+#define HAS_ILLEGAL_MEMORY_ACCESS_EXCEPTION
+#define HAS_EXTRA_EXCEPTION_INFO
+#define CPU_ID_SIZE 1
+#define CPU_ID_VALUE 0x0
+#define HARDWARE_DIVIDE_PRESENT 1
+#define HARDWARE_MULTIPLY_PRESENT 1
+#define HARDWARE_MULX_PRESENT 0
+#define INST_ADDR_WIDTH 29
+#define DATA_ADDR_WIDTH 29
+
+/*
+ * Macros for device 'cfi_flash_64m', class 'altera_avalon_cfi_flash'
+ * The macros are prefixed with 'CFI_FLASH_64M_'.
+ * The prefix is the slave descriptor.
+ */
+#define CFI_FLASH_64M_BASE 0x0
+#define CFI_FLASH_64M_SPAN 67108864u
+#define CFI_FLASH_64M_SETUP_VALUE 75
+#define CFI_FLASH_64M_WAIT_VALUE 35
+#define CFI_FLASH_64M_HOLD_VALUE 1
+#define CFI_FLASH_64M_TIMING_UNITS "ns"
+#define CFI_FLASH_64M_SIZE 67108864u
+
+/*
+ * Macros for device 'fast_tlb_miss_ram_1k', class
'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'FAST_TLB_MISS_RAM_1K_'.
+ * The prefix is the slave descriptor.
+ */
+#define FAST_TLB_MISS_RAM_1K_BASE 0x7fff400
+#define FAST_TLB_MISS_RAM_1K_SPAN 1024u
+#define FAST_TLB_MISS_RAM_1K_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define FAST_TLB_MISS_RAM_1K_INIT_CONTENTS_FILE "fast_tlb_miss_ram_1k"
+#define FAST_TLB_MISS_RAM_1K_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define FAST_TLB_MISS_RAM_1K_GUI_RAM_BLOCK_TYPE "Automatic"
+#define FAST_TLB_MISS_RAM_1K_WRITABLE 1
+#define FAST_TLB_MISS_RAM_1K_DUAL_PORT 1
+#define FAST_TLB_MISS_RAM_1K_SIZE_VALUE 1024u
+#define FAST_TLB_MISS_RAM_1K_SIZE_MULTIPLE 1
+#define FAST_TLB_MISS_RAM_1K_CONTENTS_INFO ""
+#define FAST_TLB_MISS_RAM_1K_RAM_BLOCK_TYPE "Auto"
+#define FAST_TLB_MISS_RAM_1K_INIT_MEM_CONTENT 1
+#define FAST_TLB_MISS_RAM_1K_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define FAST_TLB_MISS_RAM_1K_INSTANCE_ID "NONE"
+#define FAST_TLB_MISS_RAM_1K_READ_DURING_WRITE_MODE "DONT_CARE"
+
+/*
+ * Macros for device 'descriptor_memory', class 'altera_avalon_onchip_memory2'
+ * The macros are prefixed with 'DESCRIPTOR_MEMORY_'.
+ * The prefix is the slave descriptor.
+ */
+#define DESCRIPTOR_MEMORY_BASE 0x8002000
+#define DESCRIPTOR_MEMORY_SPAN 8192u
+#define DESCRIPTOR_MEMORY_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
+#define DESCRIPTOR_MEMORY_INIT_CONTENTS_FILE "descriptor_memory"
+#define DESCRIPTOR_MEMORY_NON_DEFAULT_INIT_FILE_ENABLED 0
+#define DESCRIPTOR_MEMORY_GUI_RAM_BLOCK_TYPE "Automatic"
+#define DESCRIPTOR_MEMORY_WRITABLE 1
+#define DESCRIPTOR_MEMORY_DUAL_PORT 0
+#define DESCRIPTOR_MEMORY_SIZE_VALUE 8192u
+#define DESCRIPTOR_MEMORY_SIZE_MULTIPLE 1
+#define DESCRIPTOR_MEMORY_CONTENTS_INFO ""
+#define DESCRIPTOR_MEMORY_RAM_BLOCK_TYPE "Auto"
+#define DESCRIPTOR_MEMORY_INIT_MEM_CONTENT 1
+#define DESCRIPTOR_MEMORY_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
+#define DESCRIPTOR_MEMORY_INSTANCE_ID "NONE"
+#define DESCRIPTOR_MEMORY_READ_DURING_WRITE_MODE "DONT_CARE"
+
+/*
+ * Macros for device 'tse_mac', class 'triple_speed_ethernet'
+ * The macros are prefixed with 'TSE_MAC_'.
+ * The prefix is the slave descriptor.
+ */
+#define TSE_MAC_BASE 0x8004000
+#define TSE_MAC_SPAN 1024u
+#define TSE_MAC_TRANSMIT "sgdma_tx"
+#define TSE_MAC_RECEIVE "sgdma_rx"
+#define TSE_MAC_TRANSMIT_FIFO_DEPTH 2048
+#define TSE_MAC_RECEIVE_FIFO_DEPTH 2048
+#define TSE_MAC_FIFO_WIDTH 32
+#define TSE_MAC_ENABLE_MACLITE 0
+#define TSE_MAC_MACLITE_GIGE 0
+#define TSE_MAC_USE_MDIO 1
+#define TSE_MAC_NUMBER_OF_CHANNEL 0
+#define TSE_MAC_NUMBER_OF_MAC_MDIO_SHARED 0
+#define TSE_MAC_IS_MULTICHANNEL_MAC 0
+#define TSE_MAC_MDIO_SHARED 0
+#define TSE_MAC_REGISTER_SHARED 0
+#define TSE_MAC_PCS 0
+#define TSE_MAC_PCS_SGMII 0
+#define TSE_MAC_PCS_ID 0u
+
+/*
+ * Macros for device 'sgdma_rx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_RX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_RX_BASE 0x8004400
+#define SGDMA_RX_SPAN 1024u
+#define SGDMA_RX_IRQ 2
+#define SGDMA_RX_READ_BLOCK_DATA_WIDTH 32
+#define SGDMA_RX_WRITE_BLOCK_DATA_WIDTH 32
+#define SGDMA_RX_STREAM_DATA_WIDTH 32
+#define SGDMA_RX_ADDRESS_WIDTH 32
+#define SGDMA_RX_HAS_READ_BLOCK 0
+#define SGDMA_RX_HAS_WRITE_BLOCK 1
+#define SGDMA_RX_READ_BURSTCOUNT_WIDTH 4
+#define SGDMA_RX_WRITE_BURSTCOUNT_WIDTH 4
+#define SGDMA_RX_BURST_TRANSFER 0
+#define SGDMA_RX_ALWAYS_DO_MAX_BURST 1
+#define SGDMA_RX_DESCRIPTOR_READ_BURST 0
+#define SGDMA_RX_UNALIGNED_TRANSFER 0
+#define SGDMA_RX_CONTROL_SLAVE_DATA_WIDTH 32
+#define SGDMA_RX_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define SGDMA_RX_DESC_DATA_WIDTH 32
+#define SGDMA_RX_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define SGDMA_RX_STATUS_TOKEN_DATA_WIDTH 24
+#define SGDMA_RX_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define SGDMA_RX_BURST_DATA_WIDTH 8
+#define SGDMA_RX_CONTROL_DATA_WIDTH 8
+#define SGDMA_RX_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define SGDMA_RX_COMMAND_FIFO_DATA_WIDTH 104
+#define SGDMA_RX_SYMBOLS_PER_BEAT 4
+#define SGDMA_RX_IN_ERROR_WIDTH 6
+#define SGDMA_RX_OUT_ERROR_WIDTH 0
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * Path to the device is from the master group 'sgdma_rx_m_write'.
+ * The macros are prefixed with 'SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define SGDMA_RX_M_WRITE_DDR2_LO_LATENCY_128M_SPAN 134217728u
+
+/*
+ * Macros for device 'sgdma_tx', class 'altera_avalon_sgdma'
+ * The macros are prefixed with 'SGDMA_TX_'.
+ * The prefix is the slave descriptor.
+ */
+#define SGDMA_TX_BASE 0x8004800
+#define SGDMA_TX_SPAN 1024u
+#define SGDMA_TX_IRQ 3
+#define SGDMA_TX_READ_BLOCK_DATA_WIDTH 32
+#define SGDMA_TX_WRITE_BLOCK_DATA_WIDTH 32
+#define SGDMA_TX_STREAM_DATA_WIDTH 32
+#define SGDMA_TX_ADDRESS_WIDTH 32
+#define SGDMA_TX_HAS_READ_BLOCK 1
+#define SGDMA_TX_HAS_WRITE_BLOCK 0
+#define SGDMA_TX_READ_BURSTCOUNT_WIDTH 4
+#define SGDMA_TX_WRITE_BURSTCOUNT_WIDTH 4
+#define SGDMA_TX_BURST_TRANSFER 0
+#define SGDMA_TX_ALWAYS_DO_MAX_BURST 1
+#define SGDMA_TX_DESCRIPTOR_READ_BURST 0
+#define SGDMA_TX_UNALIGNED_TRANSFER 0
+#define SGDMA_TX_CONTROL_SLAVE_DATA_WIDTH 32
+#define SGDMA_TX_CONTROL_SLAVE_ADDRESS_WIDTH 8
+#define SGDMA_TX_DESC_DATA_WIDTH 32
+#define SGDMA_TX_CHAIN_WRITEBACK_DATA_WIDTH 32
+#define SGDMA_TX_STATUS_TOKEN_DATA_WIDTH 24
+#define SGDMA_TX_BYTES_TO_TRANSFER_DATA_WIDTH 16
+#define SGDMA_TX_BURST_DATA_WIDTH 8
+#define SGDMA_TX_CONTROL_DATA_WIDTH 8
+#define SGDMA_TX_ATLANTIC_CHANNEL_DATA_WIDTH 4
+#define SGDMA_TX_COMMAND_FIFO_DATA_WIDTH 104
+#define SGDMA_TX_SYMBOLS_PER_BEAT 4
+#define SGDMA_TX_IN_ERROR_WIDTH 0
+#define SGDMA_TX_OUT_ERROR_WIDTH 1
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * Path to the device is from the master group 'sgdma_tx_m_read'.
+ * The macros are prefixed with 'SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_'.
+ * The prefix is the master group descriptor and the slave descriptor.
+ */
+#define SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define SGDMA_TX_M_READ_DDR2_LO_LATENCY_128M_SPAN 134217728u
+
+/*
+ * Macros for device 'uart', class 'altera_avalon_uart'
+ * The macros are prefixed with 'UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define UART_BASE 0x8004c80
+#define UART_SPAN 32u
+#define UART_IRQ 10
+#define UART_BAUD 115200
+#define UART_DATA_BITS 8
+#define UART_FIXED_BAUD 0
+#define UART_PARITY 'N'
+#define UART_STOP_BITS 1
+#define UART_USE_CTS_RTS 0
+#define UART_USE_EOP_REGISTER 0
+#define UART_SIM_TRUE_BAUD 0
+#define UART_SIM_CHAR_STREAM ""
+#define UART_FREQ 62500000u
+
+/*
+ * Macros for device 'user_led_pio_8out', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_LED_PIO_8OUT_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_LED_PIO_8OUT_BASE 0x8004cc0
+#define USER_LED_PIO_8OUT_SPAN 16u
+#define USER_LED_PIO_8OUT_DO_TEST_BENCH_WIRING 0
+#define USER_LED_PIO_8OUT_DRIVEN_SIM_VALUE 0x0
+#define USER_LED_PIO_8OUT_HAS_TRI 0
+#define USER_LED_PIO_8OUT_HAS_OUT 1
+#define USER_LED_PIO_8OUT_HAS_IN 0
+#define USER_LED_PIO_8OUT_CAPTURE 0
+#define USER_LED_PIO_8OUT_BIT_CLEARING_EDGE_REGISTER 0
+#define USER_LED_PIO_8OUT_DATA_WIDTH 8
+#define USER_LED_PIO_8OUT_RESET_VALUE 0xff
+#define USER_LED_PIO_8OUT_EDGE_TYPE "NONE"
+#define USER_LED_PIO_8OUT_IRQ_TYPE "NONE"
+#define USER_LED_PIO_8OUT_FREQ 62500000u
+
+/*
+ * Macros for device 'user_dipsw_pio_8in', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_DIPSW_PIO_8IN_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_DIPSW_PIO_8IN_BASE 0x8004ce0
+#define USER_DIPSW_PIO_8IN_SPAN 16u
+#define USER_DIPSW_PIO_8IN_IRQ 8
+#define USER_DIPSW_PIO_8IN_DO_TEST_BENCH_WIRING 0
+#define USER_DIPSW_PIO_8IN_DRIVEN_SIM_VALUE 0x0
+#define USER_DIPSW_PIO_8IN_HAS_TRI 0
+#define USER_DIPSW_PIO_8IN_HAS_OUT 0
+#define USER_DIPSW_PIO_8IN_HAS_IN 1
+#define USER_DIPSW_PIO_8IN_CAPTURE 1
+#define USER_DIPSW_PIO_8IN_BIT_CLEARING_EDGE_REGISTER 1
+#define USER_DIPSW_PIO_8IN_DATA_WIDTH 8
+#define USER_DIPSW_PIO_8IN_RESET_VALUE 0x0
+#define USER_DIPSW_PIO_8IN_EDGE_TYPE "ANY"
+#define USER_DIPSW_PIO_8IN_IRQ_TYPE "EDGE"
+#define USER_DIPSW_PIO_8IN_FREQ 62500000u
+
+/*
+ * Macros for device 'user_pb_pio_4in', class 'altera_avalon_pio'
+ * The macros are prefixed with 'USER_PB_PIO_4IN_'.
+ * The prefix is the slave descriptor.
+ */
+#define USER_PB_PIO_4IN_BASE 0x8004d00
+#define USER_PB_PIO_4IN_SPAN 16u
+#define USER_PB_PIO_4IN_IRQ 9
+#define USER_PB_PIO_4IN_DO_TEST_BENCH_WIRING 0
+#define USER_PB_PIO_4IN_DRIVEN_SIM_VALUE 0x0
+#define USER_PB_PIO_4IN_HAS_TRI 0
+#define USER_PB_PIO_4IN_HAS_OUT 0
+#define USER_PB_PIO_4IN_HAS_IN 1
+#define USER_PB_PIO_4IN_CAPTURE 1
+#define USER_PB_PIO_4IN_BIT_CLEARING_EDGE_REGISTER 1
+#define USER_PB_PIO_4IN_DATA_WIDTH 4
+#define USER_PB_PIO_4IN_RESET_VALUE 0x0
+#define USER_PB_PIO_4IN_EDGE_TYPE "ANY"
+#define USER_PB_PIO_4IN_IRQ_TYPE "EDGE"
+#define USER_PB_PIO_4IN_FREQ 62500000u
+
+/*
+ * Macros for device 'sysid', class 'altera_avalon_sysid'
+ * The macros are prefixed with 'SYSID_'.
+ * The prefix is the slave descriptor.
+ */
+#define SYSID_BASE 0x8004d40
+#define SYSID_SPAN 8u
+#define SYSID_ID 1174346794u
+#define SYSID_TIMESTAMP 1233287581u
+
+/*
+ * Macros for device 'jtag_uart', class 'altera_avalon_jtag_uart'
+ * The macros are prefixed with 'JTAG_UART_'.
+ * The prefix is the slave descriptor.
+ */
+#define JTAG_UART_BASE 0x8004d50
+#define JTAG_UART_SPAN 8u
+#define JTAG_UART_IRQ 1
+#define JTAG_UART_WRITE_DEPTH 64
+#define JTAG_UART_READ_DEPTH 64
+#define JTAG_UART_WRITE_THRESHOLD 8
+#define JTAG_UART_READ_THRESHOLD 8
+
+/*
+ * Macros for device 'linux_timer_1ms', class 'altera_avalon_timer'
+ * The macros are prefixed with 'LINUX_TIMER_1MS_'.
+ * The prefix is the slave descriptor.
+ */
+#define LINUX_TIMER_1MS_BASE 0x8400000
+#define LINUX_TIMER_1MS_SPAN 32u
+#define LINUX_TIMER_1MS_IRQ 11
+#define LINUX_TIMER_1MS_ALWAYS_RUN 0
+#define LINUX_TIMER_1MS_FIXED_PERIOD 0
+#define LINUX_TIMER_1MS_SNAPSHOT 1
+#define LINUX_TIMER_1MS_PERIOD 1
+#define LINUX_TIMER_1MS_PERIOD_UNITS "ms"
+#define LINUX_TIMER_1MS_RESET_OUTPUT 0
+#define LINUX_TIMER_1MS_TIMEOUT_PULSE_OUTPUT 0
+#define LINUX_TIMER_1MS_FREQ 125000000u
+#define LINUX_TIMER_1MS_LOAD_VALUE 124999ULL
+#define LINUX_TIMER_1MS_COUNTER_SIZE 32
+#define LINUX_TIMER_1MS_MULT 0.0010
+#define LINUX_TIMER_1MS_TICKS_PER_SEC 1000u
+
+/*
+ * Macros for device 'ddr2_lo_latency_128m', class 'altmemddr2'
+ * The macros are prefixed with 'DDR2_LO_LATENCY_128M_'.
+ * The prefix is the slave descriptor.
+ */
+#define DDR2_LO_LATENCY_128M_BASE 0x10000000
+#define DDR2_LO_LATENCY_128M_SPAN 134217728
+
+
+#endif /* _ALTERA_LINUX_CPU_H_ */
diff --git a/include/configs/EP3C120.h b/include/configs/EP3C120.h
new file mode 100644
index 0000000..4624102
--- /dev/null
+++ b/include/configs/EP3C120.h
@@ -0,0 +1,394 @@
+/*
+ * (C) Copyright 2005, Psyent Corporation <www.psyent.com>
+ * Scott McNutt <smcn...@psyent.com>
+ * (C) Copyright 2010, Thomas Chou <tho...@wytron.com.tw>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * BOARD/CPU
+ */
+#include "../board/altera/nios2-generic/default_mmu.h"
+#define CONFIG_BOARD_NAME "EP3C120"
+#define CONFIG_EP3C120
+
+#define CONFIG_SYS_CLK_FREQ 125000000
+#define CONFIG_SYS_RESET_ADDR RESET_ADDR
+#define CONFIG_SYS_EXCEPTION_ADDR EXCEPTION_ADDR
+#define CONFIG_BOARD_EARLY_INIT_F /* enable early board-spec. init */
+#define CONFIG_BOARD_LATE_INIT /* enable late board-spec. init */
+
+#ifndef KERNEL_REGION_BASE
+# define KERNEL_REGION_BASE 0 /* NOMMU */
+#endif
+
+#ifndef IO_REGION_BASE
+# define IO_REGION_BASE 0x80000000 /* NOMMU */
+#endif
+
+/*
+ * CACHE -- the following will support II/s and II/f. The II/s does not
+ * have dcache, so the cache instructions will behave as NOPs.
+ */
+#define CONFIG_SYS_ICACHE_SIZE ICACHE_SIZE
+#define CONFIG_SYS_ICACHELINE_SIZE ICACHE_LINE_SIZE
+#define CONFIG_SYS_DCACHE_SIZE DCACHE_SIZE
+#define CONFIG_SYS_DCACHELINE_SIZE DCACHE_LINE_SIZE
+
+/*
+ * MEMORY BASE ADDRESSES
+ */
+#define CONFIG_SYS_SDRAM_BASE (DDR2_LO_LATENCY_128M_BASE | KERNEL_REGION_BASE)
+#define CONFIG_SYS_SDRAM_SIZE (DDR2_LO_LATENCY_128M_SPAN)
+
+/*
+ * GPIO
+ */
+#define CONFIG_SYS_GPIO_BASE (GPIO_BASE | IO_REGION_BASE)
+#ifdef CONFIG_SYS_GPIO_BASE
+# define CONFIG_SYS_GPIO_SDA 0
+# define CONFIG_SYS_GPIO_SCL 1
+# define CONFIG_SYS_GPIO_NRB 2
+# define CONFIG_SYS_GPIO_HBT 3
+#endif
+
+/*
+ * Flash Settings
+ */
+/* #define CONFIG_SYS_NO_FLASH */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_FLASH_CFI_MTD
+
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */
+#define CONFIG_SYS_FLASH_BASE (CFI_FLASH_64M_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 512
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * SPI FLash,EPCS Settings
+ */
+/* #define CONFIG_CMD_SPI */
+/* #define CONFIG_CMD_SF */
+/* #define CONFIG_SPI_FLASH */
+/* #define CONFIG_ALTERA_SPI */
+
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE ((EPCS_CONTROLLER_BASE + \
+ EPCS_CONTROLLER_REGISTER_OFFSET) \
+ | IO_REGION_BASE)
+
+/*
+ * NAND Flash
+ */
+/* #define CONFIG_CMD_NAND */
+/* #define CONFIG_NAND_PLAT */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE (NAND_FLASH_BASE | IO_REGION_BASE)
+#define NIOS2_NAND_PLAT_CLE 2
+#define NIOS2_NAND_PLAT_ALE 3
+#define NAND_PLAT_WRITE_CMD(chip, cmd) \
+ writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+ (1 << NIOS2_NAND_PLAT_CLE))
+#define NAND_PLAT_WRITE_ADR(chip, cmd) \
+ writeb(cmd, (unsigned int)(this->IO_ADDR_W) + \
+ (1 << NIOS2_NAND_PLAT_ALE))
+#define NAND_PLAT_INIT() {}
+#ifdef CONFIG_SYS_GPIO_NRB
+# define NAND_PLAT_DEV_READY(chip) \
+ readl(CONFIG_SYS_GPIO_BASE + ((CONFIG_SYS_GPIO_NRB) << 2))
+#endif
+
+/*
+ * SERIAL
+ */
+/* #define CONFIG_ALTERA_UART */
+#define CONFIG_ALTERA_JTAG_UART
+
+#if defined(CONFIG_ALTERA_JTAG_UART)
+#define CONFIG_SYS_NIOS_CONSOLE (JTAG_UART_BASE | IO_REGION_BASE)
+#else
+#define CONFIG_SYS_NIOS_CONSOLE (UART_BASE | IO_REGION_BASE)
+#endif
+
+#define CONFIG_ALTERA_JTAG_UART_BYPASS
+#define CONFIG_SYS_UART_FREQ UART_FREQ
+#define CONFIG_BAUDRATE UART_BAUD /* Initial baudrate */
+#define CONFIG_SYS_BAUDRATE_TABLE {UART_BAUD}
+#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info */
+
+/*
+ * SYSID
+ */
+#define CONFIG_SYS_NIOS_SYSID_BASE (SYSID_BASE | IO_REGION_BASE)
+
+/*
+ * TIMER
+ */
+#define CONFIG_SYS_NIOS_TMRBASE (LINUX_TIMER_1MS_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_NIOS_TMRIRQ LINUX_TIMER_1MS_IRQ
+#define CONFIG_SYS_NIOS_TMRCNT ((LINUX_TIMER_1MS_FREQ / \
+ CONFIG_SYS_HZ) - 1)
+#define CONFIG_SYS_HZ 100
+
+/*
+ * STATUS LED
+ */
+#define CONFIG_STATUS_LED /* Enable status driver */
+#define CONFIG_EPLED /* Enable LED PIO driver */
+#define CONFIG_SYS_LEDPIO_ADDR (USER_LED_PIO_8OUT_BASE | \
+ IO_REGION_BASE)
+
+#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
+#define STATUS_LED_STATE 1 /* Blinking */
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* 500 mS */
+
+/*
+ * IDE support
+ */
+/* #define CONFIG_CMD_IDE */
+
+#define CONFIG_SYS_PIO_MODE 1
+#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
+#define CONFIG_SYS_IDE_MAXDEVICE 1
+#define CONFIG_SYS_ATA_BASE_ADDR (CF_IDE_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ATA_STRIDE 4 /* 1bit shift */
+#define CONFIG_SYS_ATA_DATA_OFFSET 0x0 /* data reg offset */
+#define CONFIG_SYS_ATA_REG_OFFSET 0x0 /* reg offset */
+#define CONFIG_SYS_ATA_ALT_OFFSET 0x20 /* alternate register offset */
+#define CONFIG_SYS_CF_CTL_BASE (CF_CTL_BASE | IO_REGION_BASE)
+#define CONFIG_IDE_RESET
+
+/*
+ * ETHERNET
+ */
+/* #define CONFIG_SMC91111 */
+#define CONFIG_SMC91111_BASE ((ENET_BASE + ENET_LAN91C111_REGISTERS_OFFSET) \
+ | IO_REGION_BASE) /* Base addr */
+#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
+#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */
+
+/* #define CONFIG_DRIVER_DM9000 */
+#define CONFIG_DM9000_BASE (DM9000_BASE | IO_REGION_BASE)
+#define DM9000_IO CONFIG_DM9000_BASE
+#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
+#define CONFIG_DM9000_USE_16BIT 1
+#define CONFIG_DM9000_NO_SROM 1
+/* #define CONFIG_NET_RETRY_COUNT 20 */
+/* #define CONFIG_RESET_PHY_R 1 */
+
+#define CONFIG_ALTERA_TSE
+#define CONFIG_MII 1
+#define CONFIG_CMD_MII
+#define CONFIG_ETHPRIME "tse0"
+#undef CONFIG_PCI
+
+#define CONFIG_SYS_NUM_TSE_MACS 1
+#define CONFIG_SYS_ALTERA_TSE_0_NAME "tse0"
+#define CONFIG_SYS_ALTERA_TSE_0_BASE (TSE_MAC_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_BASE (SGDMA_RX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_BASE (SGDMA_TX_BASE | IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_RX_IRQ SGDMA_RX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_SGDMA_TX_IRQ SGDMA_TX_IRQ
+#define CONFIG_SYS_ALTERA_TSE_0_HAS_DESC_MEM 0
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_BASE (DESCRIPTOR_MEMORY_BASE | \
+ IO_REGION_BASE)
+#define CONFIG_SYS_ALTERA_TSE_0_DESC_MEM_SPAN DESCRIPTOR_MEMORY_SPAN
+#define CONFIG_SYS_ALTERA_TSE_0_RXFIFO_DEPTH TSE_MAC_RECEIVE_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_TXFIFO_DEPTH TSE_MAC_TRANSMIT_FIFO_DEPTH
+#define CONFIG_SYS_ALTERA_TSE_0_PHY_ADDR 18
+
+/* TSE Supported modes */
+/* GMII/MII = 0 */
+/* RGMII = 1 */
+/* RGMII_ID = 2 */
+/* RGMII_TXID = 3 */
+/* RGMII_RXID = 4 */
+/* SGMII = 5 */
+#define CONFIG_SYS_ALTERA_TSE_0_FLAGS 0x0
+
+/* #define CONFIG_ETHOC */
+#define CONFIG_SYS_ETHOC_BASE (IGOR_MAC_BASE | IO_REGION_BASE)
+
+#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
+#define CONFIG_NETMASK 255.255.255.0
+#define CONFIG_IPADDR 192.168.1.10
+#define CONFIG_GWADDR 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.1
+#define CONFIG_BOOTDELAY 10
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_BOOTD
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_ITEST
+#undef CONFIG_CMD_NFS
+#undef CONFIG_CMD_SETGETDCR
+#undef CONFIG_CMD_XIMG
+
+#ifdef CONFIG_CMD_NET
+# define CONFIG_NET_MULTI
+# define CONFIG_CMD_DHCP
+# define CONFIG_CMD_PING
+#endif
+
+#define CONFIG_CMD_SAVES
+#define CONFIG_CMD_JFFS2
+#define CONFIG_JFFS2_CMDLINE
+/* #define CONFIG_CMD_FAT */
+/* #define CONFIG_DOS_PARTITION */
+/* #define CONFIG_CMD_UBI */
+/* #define CONFIG_CMD_UBIFS */
+/* #define CONFIG_RBTREE */
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_CMD_MTDPARTS
+/* #define CONFIG_LZO */
+
+/*
+ * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
+ * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the
+ * reset address, no? This will keep the environment in user region
+ * of flash. NOTE: the monitor length must be multiple of sector size
+ * (which is common practice).
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+/* #define CONFIG_ENV_IS_IN_SPI_FLASH */
+/* #define CONFIG_ENV_IS_IN_NAND */
+
+#if defined(CONFIG_ENV_IS_IN_FLASH)
+# define CONFIG_ENV_SIZE 0x20000 /* 1 sector */
+# define CONFIG_ENV_OVERWRITE /* Serial change Ok */
+# define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \
+ CONFIG_SYS_MONITOR_LEN) | \
+ IO_REGION_BASE)
+#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH)
+# define CONFIG_ENV_OFFSET 0x7e0000 /* last sector */
+# define CONFIG_ENV_SIZE 0x20000 /* 1 sector */
+# define CONFIG_ENV_SECT_SIZE 0x20000
+# define CONFIG_ENV_SPI_BUS 0
+# define CONFIG_ENV_SPI_CS 0
+# define CONFIG_ENV_SPI_MAX_HZ 30000000 /*30Mhz */
+#elif defined(CONFIG_ENV_IS_IN_NAND)
+# define CONFIG_ENV_OFFSET 0x40000
+# define CONFIG_ENV_SIZE 0x40000 /* 1 sector */
+#else
+# define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
+# define CONFIG_ENV_SIZE 0x20000
+#endif
+
+/*
+ * MEMORY ORGANIZATION
+ * -Monitor at top of sdram.
+ * -The heap is placed below the monitor
+ * -Global data is placed below the heap.
+ * -The stack is placed below global data (&grows down).
+ */
+#define CONFIG_MONITOR_IS_IN_RAM
+#ifdef CONFIG_CMD_UBI
+# define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
+#else
+# define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256k */
+#endif
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE - \
+ CONFIG_SYS_MONITOR_LEN)
+#define CONFIG_SYS_GBL_DATA_SIZE 256 /* Global data size rsvd */
+#ifdef CONFIG_CMD_UBI /* UBI needs >512KB malloc */
+# define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x100000)
+#else
+# define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x20000)
+#endif
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - \
+ CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
+
+/*
+ * MISC
+ */
+#define CONFIG_SYS_LONGHELP /* Provide extended help */
+#define CONFIG_SYS_PROMPT "==> " /* Command prompt */
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */
+#define CONFIG_SYS_MAXARGS 16 /* Max command args */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Bootarg buf size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + \
+ 16) /* Print buf size */
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_INIT_SP - 0x20000)
+
+#if defined(CONFIG_NAND_PLAT)
+# define MTD_ENV_SETTINGS \
+ "mtdids=nand0=nand0\0" \
+ "mtdparts=mtdparts=nand0:-(data)\0"
+#elif defined(CONFIG_FLASH_CFI_DRIVER)
+# define MTD_ENV_SETTINGS \
+ "mtdids=nor0=ep3c120-flash\0" \
+ "mtdparts=mtdparts=ep3c120-flash:40m(JFFS),1M(U-Boot),4m(uImage1)," \
+ "4m(uImage2),4m(uImage3),3584k(DEFAULT_MMU),3584k(MAXIMUM_MMU),"\
+ "3584k(USER_IMAGE),512k(options-bits)\0"
+#else
+# define MTD_ENV_SETTINGS
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ MTD_ENV_SETTINGS \
+ "autoload=no\0" \
+ "autostart=no\0" \
+ "bootcmd=run tftp_program_flash\0" \
+ "ipaddr_cmd=" \
+ "echo 'Getting ethaddr from flash';" \
+ "altera ethaddr;" \
+ "echo 'DHCP Address';" \
+ "dhcp;" \
+ "run set_serverip\0" \
+ "tftp_program_flash=" \
+ "echo 'TFTP Program Flash';" \
+ "run ipaddr_cmd;" \
+ "tftp 0xd1000000 ${serverip}:tftp_program_flash_script.img;" \
+ "iminfo ${fileaddr};" \
+ "autoscr ${fileaddr};\0" \
+ "set_serverip=setenv serverip ${tftpserverip}\0" \
+ "tftpserverip=137.57.185.173\0" \
+ ""
+
+#define CONFIG_CMDLINE_EDITING
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#endif
+
+#endif /* __CONFIG_H */
--
1.6.6.1
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