From: Pankit Garg <pankit.g...@nxp.com>
Change tlb base address from OCRAM to DDR when exception level is
less than 3.
Signed-off-by: Ruchika Gupta <ruchika.gu...@nxp.com>
Signed-off-by: Pankit Garg <pankit.g...@nxp.com>
---
Change in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index bae50f68d8..6304825180 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -371,7 +371,10 @@ static inline void early_mmu_setup(void)
unsigned int el = current_el();
/* global data is already setup, no allocation yet */
- gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ if (el == 3)
+ gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ else
+ gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
--
2.17.1
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