On 25.09.2018 15:17, Gregory CLEMENT wrote: > On some platforms, as the Ocelot ones, when wanting to control the CS > through software, it is not possible to do it through the GPIO > controller. Indeed, this signal is managed through a dedicated range of > registers inside the SoC..
and why did you add a spi-bitbang-gpio driver?
>
> By declaring the external_cs_manage function as weak, it is possible to
> manage the CS at platform level and then using the appropriate registers.
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com>
> ---
> drivers/spi/designware_spi.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> index d8b73ea326..fe6e753bff 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
> return 0;
> }
>
> -static void external_cs_manage(struct udevice *dev, bool on)
> +/*
> + * We define external_cs_manage function as 'weak' as some targets
> + * (like OCELOT) don't control the external CS pin using a GPIO
> + * controller. These SoCs use specific registers to controll by
> + * software the SPI pins (and especially the CS).
> + */
> +__weak void external_cs_manage(struct udevice *dev, bool on)
> {
> #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
> struct dw_spi_priv *priv = dev_get_priv(dev->parent);
>
--
- Daniel
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