On 25.09.2018 15:01, Gregory CLEMENT wrote: > Add common configuration header for the VCore III SoCs (currently Ocelot > and Luton), but also the defconfig for the evaluation boards of these > SoCs. > > Signed-off-by: Gregory CLEMENT <gregory.clem...@bootlin.com> > --- > configs/mscc_luton_defconfig | 66 +++++++++++++++++++++++++ > configs/mscc_ocelot_defconfig | 57 ++++++++++++++++++++++ > configs/mscc_ocelot_pcb120_defconfig | 56 ++++++++++++++++++++++ > include/configs/vcoreiii.h | 72 ++++++++++++++++++++++++++++ > 4 files changed, 251 insertions(+) > create mode 100644 configs/mscc_luton_defconfig > create mode 100644 configs/mscc_ocelot_defconfig > create mode 100644 configs/mscc_ocelot_pcb120_defconfig > create mode 100644 include/configs/vcoreiii.h
should also be added along with the board code > > diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig > new file mode 100644 > index 0000000000..47fe12b6ee > --- /dev/null > +++ b/configs/mscc_luton_defconfig > @@ -0,0 +1,66 @@ > +CONFIG_MIPS=y > +CONFIG_SYS_TEXT_BASE=0x40000000 > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_DEBUG_UART_BOARD_INIT=y > +CONFIG_DEBUG_UART_BASE=0x70100000 > +CONFIG_DEBUG_UART_CLOCK=208333333 > +CONFIG_ARCH_MSCC=y > +CONFIG_TARGET_LUTON_PCB091=y > +CONFIG_DDRTYPE_MT47H128M8HQ=y > +CONFIG_SYS_LITTLE_ENDIAN=y > +CONFIG_MIPS_BOOT_FDT=y > +CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" > +CONFIG_DEBUG_UART=y > +CONFIG_FIT=y > +CONFIG_BOOTDELAY=3 > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200" > +CONFIG_LOGLEVEL=7 > +CONFIG_DISPLAY_CPUINFO=y > +CONFIG_SYS_PROMPT="pcb091 # " > +# CONFIG_CMD_BDI is not set > +# CONFIG_CMD_CONSOLE is not set > +# CONFIG_CMD_ELF is not set > +# CONFIG_CMD_EXPORTENV is not set > +# CONFIG_CMD_IMPORTENV is not set > +# CONFIG_CMD_CRC32 is not set > +CONFIG_CMD_MD5SUM=y > +CONFIG_CMD_MEMINFO=y > +CONFIG_CMD_MEMTEST=y > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_DHCP=y > +# CONFIG_NET_TFTP_VARS is not set > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_PING=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" > +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_EMBED=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_CLK=y > +CONFIG_DM_GPIO=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_BAR=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_STMICRO=y > +CONFIG_SPI_FLASH_WINBOND=y > +CONFIG_SPI_FLASH_MTD=y > +CONFIG_DM_ETH=y > +CONFIG_PINCTRL=y > +CONFIG_PINCONF=y > +CONFIG_DM_SERIAL=y > +CONFIG_DEBUG_UART_SHIFT=2 > +CONFIG_SYS_NS16550=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_SOFT_SPI=y > +CONFIG_LZMA=y > +CONFIG_XZ=y > diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig > new file mode 100644 > index 0000000000..eb0566189a > --- /dev/null > +++ b/configs/mscc_ocelot_defconfig > @@ -0,0 +1,57 @@ > +CONFIG_MIPS=y > +CONFIG_SYS_TEXT_BASE=0x40000000 > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_ARCH_MSCC=y > +CONFIG_TARGET_OCELOT_PCB123=y > +CONFIG_SYS_LITTLE_ENDIAN=y > +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" > +CONFIG_FIT=y > +CONFIG_BOOTDELAY=3 > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200" > +CONFIG_LOGLEVEL=7 > +CONFIG_DISPLAY_CPUINFO=y > +CONFIG_SYS_PROMPT="pcb123 # " > +# CONFIG_CMD_BDI is not set > +# CONFIG_CMD_CONSOLE is not set > +# CONFIG_CMD_ELF is not set > +# CONFIG_CMD_EXPORTENV is not set > +# CONFIG_CMD_IMPORTENV is not set > +# CONFIG_CMD_CRC32 is not set > +CONFIG_CMD_MD5SUM=y > +CONFIG_CMD_MEMINFO=y > +CONFIG_CMD_MEMTEST=y > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_DHCP=y > +# CONFIG_NET_TFTP_VARS is not set > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_PING=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" > +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_EMBED=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_CLK=y > +CONFIG_DM_GPIO=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_BAR=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_WINBOND=y > +CONFIG_SPI_FLASH_MTD=y > +CONFIG_DM_ETH=y > +CONFIG_PINCTRL=y > +CONFIG_PINCONF=y > +CONFIG_DM_SERIAL=y > +CONFIG_SYS_NS16550=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_DESIGNWARE_SPI=y > +CONFIG_LZMA=y > diff --git a/configs/mscc_ocelot_pcb120_defconfig > b/configs/mscc_ocelot_pcb120_defconfig > new file mode 100644 > index 0000000000..40cdec45f1 > --- /dev/null > +++ b/configs/mscc_ocelot_pcb120_defconfig > @@ -0,0 +1,56 @@ > +CONFIG_MIPS=y > +CONFIG_SYS_TEXT_BASE=0x40000000 > +CONFIG_SYS_MALLOC_F_LEN=0x2000 > +CONFIG_ARCH_MSCC=y > +CONFIG_SYS_LITTLE_ENDIAN=y > +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120" > +CONFIG_FIT=y > +CONFIG_BOOTDELAY=3 > +CONFIG_USE_BOOTARGS=y > +CONFIG_BOOTARGS="console=ttyS0,115200" > +CONFIG_LOGLEVEL=7 > +CONFIG_DISPLAY_CPUINFO=y > +CONFIG_SYS_PROMPT="pcb120 # " > +# CONFIG_CMD_BDI is not set > +# CONFIG_CMD_CONSOLE is not set > +# CONFIG_CMD_ELF is not set > +# CONFIG_CMD_EXPORTENV is not set > +# CONFIG_CMD_IMPORTENV is not set > +# CONFIG_CMD_CRC32 is not set > +CONFIG_CMD_MD5SUM=y > +CONFIG_CMD_MEMINFO=y > +CONFIG_CMD_MEMTEST=y > +# CONFIG_CMD_FLASH is not set > +CONFIG_CMD_GPIO=y > +CONFIG_CMD_SF=y > +CONFIG_CMD_SPI=y > +CONFIG_CMD_DHCP=y > +# CONFIG_NET_TFTP_VARS is not set > +# CONFIG_CMD_NFS is not set > +CONFIG_CMD_PING=y > +CONFIG_CMD_MTDPARTS=y > +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" > +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" > +# CONFIG_ISO_PARTITION is not set > +CONFIG_OF_EMBED=y > +CONFIG_ENV_IS_IN_SPI_FLASH=y > +CONFIG_NET_RANDOM_ETHADDR=y > +CONFIG_CLK=y > +CONFIG_DM_GPIO=y > +CONFIG_DM_SPI_FLASH=y > +CONFIG_SPI_FLASH=y > +CONFIG_SPI_FLASH_BAR=y > +CONFIG_SPI_FLASH_GIGADEVICE=y > +CONFIG_SPI_FLASH_MACRONIX=y > +CONFIG_SPI_FLASH_SPANSION=y > +CONFIG_SPI_FLASH_WINBOND=y > +CONFIG_SPI_FLASH_MTD=y > +CONFIG_DM_ETH=y > +CONFIG_PINCTRL=y > +CONFIG_PINCONF=y > +CONFIG_DM_SERIAL=y > +CONFIG_SYS_NS16550=y > +CONFIG_SPI=y > +CONFIG_DM_SPI=y > +CONFIG_DESIGNWARE_SPI=y > +CONFIG_LZMA=y > diff --git a/include/configs/vcoreiii.h b/include/configs/vcoreiii.h > new file mode 100644 > index 0000000000..ce43a27d7d > --- /dev/null > +++ b/include/configs/vcoreiii.h > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 Microsemi Corporation > + */ > + > +#ifndef __VCOREIII_H > +#define __VCOREIII_H > + > +#include <linux/sizes.h> > + > +/* Onboard devices */ > + > +#define CONFIG_SYS_MALLOC_LEN 0x80000 > +#define CONFIG_SYS_LOAD_ADDR 0x00100000 > +#define CONFIG_SYS_INIT_SP_OFFSET 0x400000 > + > +#define CPU_CLOCK_RATE 500000000 /* Clock for the MIPS > core */ > +#ifdef CONFIG_SOC_LUTON > +#define CONFIG_SYS_MIPS_TIMER_FREQ 208333333 > +#else > +#define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_CLOCK_RATE / 2) > +#endif > +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_MIPS_TIMER_FREQ > + > +#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET) > +#define CONFIG_ENV_OFFSET (512 * 1024) > +#define CONFIG_ENV_SIZE (256 * 1024) > +#define CONFIG_ENV_SECT_SIZE (256 * 1024) > +#endif > + > +#define CONFIG_SYS_SDRAM_BASE 0x80000000 > +#if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) || > defined(CONFIG_DDRTYPE_MT47H128M8HQ) > +#define CONFIG_SYS_SDRAM_SIZE (128 * SZ_1M) > +#elif defined(CONFIG_DDRTYPE_MT41J128M16HA) || > defined(CONFIG_DDRTYPE_MT41K128M16JT) > +#define CONFIG_SYS_SDRAM_SIZE (256 * SZ_1M) > +#elif defined(CONFIG_DDRTYPE_H5TQ4G63MFR) || > defined(CONFIG_DDRTYPE_MT41K256M16) > +#define CONFIG_SYS_SDRAM_SIZE (512 * SZ_1M) > +#else > +#error Unknown DDR size - please add! > +#endif > + > +#define CONFIG_CONS_INDEX 1 > + > +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + > CONFIG_SYS_SDRAM_SIZE - SZ_1M) > + > +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of > monitor */ > + > +#define CONFIG_BOARD_EARLY_INIT_R > +#if defined (CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT) > +#define VCOREIII_DEFAULT_MTD_ENV \ > + "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ > + "mtdids="CONFIG_MTDIDS_DEFAULT "\0" > +#else > +#define VCOREIII_DEFAULT_MTD_ENV // Go away > +#endif > + > +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip > size */ > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + VCOREIII_DEFAULT_MTD_ENV \ > + "loadaddr=0x81000000" "\0" \ > + "spi_image_off=0x00100000" "\0" \ > + "console=ttyS0,115200" "\0" \ > + "setup=setenv bootargs console=${console} ${mtdparts} ${bootargs_extra}" > "\0" \ > + "spiboot=run setup; sf probe; sf read ${loadaddr} ${spi_image_off} > 0x600000; bootm ${loadaddr}" "\0" \ > + "update=sf probe;mtdparts;dhcp ${loadaddr} u-boot.bin;" \ > + "sf erase UBoot 0x080000;sf write ${loadaddr} UBoot ${filesize}" "\0" \ > + "initrd_high=0x9000000" \ > + "bootcmd=run spiboot" > + > +#endif /* __VCOREIII_H */ > -- - Daniel
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