On 31.08.2018 16:28, Quentin Schulz wrote:
The SSP2 clock is at bit 6 in the register, so the value is 0x40 unlike
the current 0x70 which enables the clock of UART2, SSP1 and SSP2.
Signed-off-by: Quentin Schulz <quentin.sch...@bootlin.com>
---
added in v2
@Stefan: I think you'd want to test the FPGA on x600 again as it's using
this constant. Having worked on a system close to the x600, I'm guessing
that it'll work as fine as on my platform with this patch but better be
sure than sorry.
I don't have easily access to the x600 board right now. Please go ahead
with this patch. I'm now informed about this change and will make some
tests, if I get this board on my desk again.
Acked-by: Stefan Roese <s...@denx.de>
Thanks,
Stefan
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