Hi Marek,
2018-08-21 22:57 GMT+09:00 Marek Vasut <ma...@denx.de>:
> Add optional reset support into the Denali NAND driver. In case there is
> a valid reset entry in the DT, the reset gets deasserted before the NAND
> controller gets used.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Masahiro Yamada <yamada.masah...@socionext.com>
> ---
> drivers/mtd/nand/denali_dt.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mtd/nand/denali_dt.c b/drivers/mtd/nand/denali_dt.c
> index 65a7797f0f..6fcd7d3843 100644
> --- a/drivers/mtd/nand/denali_dt.c
> +++ b/drivers/mtd/nand/denali_dt.c
> @@ -9,6 +9,7 @@
> #include <linux/io.h>
> #include <linux/ioport.h>
> #include <linux/printk.h>
> +#include <reset.h>
>
> #include "denali.h"
>
> @@ -64,6 +65,7 @@ static int denali_dt_probe(struct udevice *dev)
> const struct denali_dt_data *data;
> struct clk clk;
> struct resource res;
> + struct reset_ctl reset_ctl;
> int ret;
>
> data = (void *)dev_get_driver_data(dev);
> @@ -97,6 +99,13 @@ static int denali_dt_probe(struct udevice *dev)
>
> denali->clk_x_rate = clk_get_rate(&clk);
>
> + ret = reset_get_by_index(dev, 0, &reset_ctl);
> + if (!ret) {
> + reset_assert(&reset_ctl);
> + udelay(2);
> + reset_deassert(&reset_ctl);
> + }
> +
> return denali_init(denali);
> }
>
I was testing this patch today
because my SoC also has a reset line for NAND.
This patch looks trivial enough,
but if the NAND is reset here,
my board fails to boot with
"nand_base: timeout while waiting for chip to become ready"
I do not know why.
Please give me more time to figure out what is going on in my SoC.
U-Boot SPL 2018.09-rc2-00106-g5f0d7e5-dirty (Aug 24 2018 - 22:00:33 +0900)
Trying to boot from NOR
U-Boot 2018.09-rc2-00106-g5f0d7e5-dirty (Aug 24 2018 - 22:00:33 +0900)
SoC: LD4 (model 1, revision 3)
Model: UniPhier LD4 Reference Board
DRAM: 512 MiB
SC: Micro Support Card (CPLD version 3.6)
NAND: nand_base: timeout while waiting for chip to become ready
--
Best Regards
Masahiro Yamada
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