The patch converts the pk1c20 board to use the common cfi flash
and spi driver.
The addressing of devices is changed to virtual address.
The args to writel() is changed to (val,port) in led.c.
Signed-off-by: Thomas Chou <tho...@wytron.com.tw>
---
board/psyent/pk1c20/Makefile | 2 +-
board/psyent/pk1c20/config.mk | 2 +-
board/psyent/pk1c20/led.c | 12 +++---
board/psyent/pk1c20/u-boot.lds | 1 +
include/configs/PK1C20.h | 68 ++++++++++++++++++++++++++--------------
5 files changed, 53 insertions(+), 32 deletions(-)
diff --git a/board/psyent/pk1c20/Makefile b/board/psyent/pk1c20/Makefile
index e23a17b..84db953 100644
--- a/board/psyent/pk1c20/Makefile
+++ b/board/psyent/pk1c20/Makefile
@@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).a
-COMOBJS := ../common/AMDLV065D.o
+COMOBJS :=
COBJS := $(BOARD).o led.o $(COMOBJS)
diff --git a/board/psyent/pk1c20/config.mk b/board/psyent/pk1c20/config.mk
index d65780d..ff49287 100644
--- a/board/psyent/pk1c20/config.mk
+++ b/board/psyent/pk1c20/config.mk
@@ -21,7 +21,7 @@
# MA 02111-1307 USA
#
-TEXT_BASE = 0x01fc0000
+#TEXT_BASE = 0x01fc0000
PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul
PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
index e5e7705..d092011 100644
--- a/board/psyent/pk1c20/led.c
+++ b/board/psyent/pk1c20/led.c
@@ -33,30 +33,30 @@ static led_id_t val = 0;
void __led_init (led_id_t mask, int state)
{
- nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+ nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_set (led_id_t mask, int state)
{
- nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+ nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE;
if (state == STATUS_LED_ON)
val &= ~mask;
else
val |= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
void __led_toggle (led_id_t mask)
{
- nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
+ nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LED_PIO_BASE;
val ^= mask;
- writel (&pio->data, val);
+ writel (val, &pio->data);
}
diff --git a/board/psyent/pk1c20/u-boot.lds b/board/psyent/pk1c20/u-boot.lds
index b2d88a5..5c26351 100644
--- a/board/psyent/pk1c20/u-boot.lds
+++ b/board/psyent/pk1c20/u-boot.lds
@@ -28,6 +28,7 @@ ENTRY(_start)
SECTIONS
{
+ . = text_base;
.text :
{
cpu/nios2/start.o (.text)
diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h
index cf6f7a9..3cd0806 100644
--- a/include/configs/PK1C20.h
+++ b/include/configs/PK1C20.h
@@ -24,6 +24,9 @@
#ifndef __CONFIG_H
#define __CONFIG_H
+#define CONFIG_SYS_BOARD_NAME "Psyent PK1C20"
+#define IO_REGION_BASE 0x80000000
+
/*------------------------------------------------------------------------
* BOARD/CPU
*----------------------------------------------------------------------*/
@@ -32,7 +35,7 @@
#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address
*/
#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry
point*/
-#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address
*/
+#define CONFIG_SYS_NIOS_SYSID_BASE 0x821208b8 /* System id address
*/
#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
@@ -47,7 +50,7 @@
/*------------------------------------------------------------------------
* MEMORY BASE ADDRESSES
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr
*/
+#define CONFIG_SYS_FLASH_BASE 0x80000000 /* FLASH base addr
*/
#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte
*/
#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr
*/
#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte
*/
@@ -61,23 +64,29 @@
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k
*/
+#define CONFIG_SYS_TEXT_LEN (256 * 1024) /* Reserve 256k */
+#define CONFIG_SYS_TEXT_BASE (CONFIG_SYS_SDRAM_BASE + \
+ CONFIG_SYS_SDRAM_SIZE -
CONFIG_SYS_TEXT_LEN)
+#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_RESET_ADDR |
IO_REGION_BASE)
+#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_TEXT_LEN
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size
rsvd*/
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
-#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE -
CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_TEXT_BASE -
CONFIG_SYS_MALLOC_LEN)
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE -
CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix nios2 flash timing issue in
amd toggle*/
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank
*/
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks
*/
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec)
*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec)
*/
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size
*/
/*------------------------------------------------------------------------
* ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above
@@ -95,13 +104,16 @@
* CONSOLE
*----------------------------------------------------------------------*/
#if defined(CONFIG_CONSOLE_JTAG)
-#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr
*/
+#define CONFIG_ALTERA_JTAGUART
#else
-#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr
*/
+#define CONFIG_ALTERA_UART
#endif
-#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed
*/
-#define CONFIG_BAUDRATE 115200 /* Initial baudrate
*/
+#define CONFIG_SYS_JTAGUART_BASE 0x821208b0 /* JTAG UART base addr
*/
+#define CONFIG_SYS_UART_BASE 0x82120840 /* UART base addr
*/
+
+#define CONFIG_SYS_UART_FREQ CONFIG_SYS_CLK_FREQ
+#define CONFIG_BAUDRATE 115200 /* Initial
baudrate */
#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-)
*/
#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console
info*/
@@ -112,7 +124,15 @@
* _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK.
* The register base is currently at offset 0x600 from the memory base.
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base
*/
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_ALTERA_SPI
+
+#define CONFIG_ENV_SPI_MAX_HZ 30000000
+#define CONFIG_SF_DEFAULT_SPEED 30000000
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_SYS_SPI_BASE 0x82100200 /* EPCS register base
*/
/*------------------------------------------------------------------------
* DEBUG
@@ -126,23 +146,23 @@
* registers, we can slow it down to 10 msec using TMRCNT. If the default
* period is acceptable, TMRCNT can be left undefined.
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr
*/
-#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num
*/
-#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick
*/
-#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS *
(CONFIG_SYS_CLK_FREQ/1000))
-#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT +
1))
+#define CONFIG_SYS_TIMER_BASE 0x82120820 /* Tick timer base addr
*/
+#define CONFIG_SYS_TIMER_IRQ 3 /* Timer IRQ num
*/
+#define CONFIG_SYS_TIMER_FREQ CONFIG_SYS_CLK_FREQ /* Timer input
freq */
+#define CONFIG_SYS_HZ 1000 /* should be 1000 for
flash timing */
/*------------------------------------------------------------------------
* STATUS LED -- Provides a simple blinking led. For Nios2 each board
* must implement its own led routines -- leds are, after all,
* board-specific, no?
*----------------------------------------------------------------------*/
-#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr
*/
+#define CONFIG_SYS_LED_PIO_BASE 0x82120870 /* LED PIO base
addr */
+#define CONFIG_EPLED /* Enable LED PIO driver */
#define CONFIG_STATUS_LED /* Enable status driver */
#define STATUS_LED_BIT 1 /* Bit-0 on PIO */
#define STATUS_LED_STATE 1 /* Blinking */
-#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec
*/
+#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) /* Every 500 msec
*/
/*------------------------------------------------------------------------
* ETHERNET -- The header file for the SMC91111 driver hurts my eyes ...
@@ -200,7 +220,7 @@
#define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus
*/
#define CONFIG_SYS_IDE_MAXDEVICE 1 /* 1 drive per IDE bus
*/
-#define CONFIG_SYS_ATA_BASE_ADDR 0x00900800 /* ATA base addr
*/
+#define CONFIG_SYS_ATA_BASE_ADDR 0x80900800 /* ATA base addr
*/
#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 /* IDE0 offset
*/
#define CONFIG_SYS_ATA_DATA_OFFSET 0x0040 /* Data IO offset
*/
#define CONFIG_SYS_ATA_REG_OFFSET 0x0040 /* Register offset
*/
@@ -209,9 +229,9 @@
#define CONFIG_DOS_PARTITION
/* Board-specific cf regs */
-#define CONFIG_SYS_CF_PRESENT 0x00900880 /* CF Present PIO base
*/
-#define CONFIG_SYS_CF_POWER 0x00900890 /* CF Power FET PIO
base*/
-#define CONFIG_SYS_CF_ATASEL 0x009008a0 /* CF ATASEL PIO base
*/
+#define CONFIG_SYS_CF_PRESENT 0x80900880 /* CF Present PIO base
*/
+#define CONFIG_SYS_CF_POWER 0x80900890 /* CF Power FET PIO
base*/
+#define CONFIG_SYS_CF_ATASEL 0x809008a0 /* CF ATASEL PIO base
*/
#endif
--
1.6.6.1
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